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US4230504A
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Method of making implant programmable N-channel ROM
Assignee: Texas Instruments Inc
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Filing: 1978-04-27
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Granted: 1980-10-28
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Expires: 1998-04-27
Abstract
Abstract An MOS read only memory or ROM is formed by a process compatible with standard N-channel silicon gate ROM manufacturing methods. Instead of moat programming or contact programming as is used in almost all standard processes, however, the ROM is programmed by implant after the polysilicon level of gates and interconnection has been deposited and patterned and prior to metal deposition. Address lines and gates are polysilicon, ground lines are defined by elongated N+ regions, and output lines are metal strips contacting the N+ diffused drains. Each potential MOS transistor in the array is programmed to be a logic "1" or "0" by ion implanting through the polysilicon gates and thin gate oxide, using patterned photoresist as a mask prior to application of the polycrystalline silicon.
Inventors
- 👤 Chang-Kiang Kuo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 11:27
CPC Classifications
G; G11; G11C; G11C17/00; G11C17/08; G11C17/10; G11C17/12; G11C17/126; H; H10; H10B; H10B20/00; H10B20/27; H10B20/30; H10B20/38; H10B20/383; H10B20/40; H10D; H10D64/00; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/512; H10D64/513
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
124 words
A method of making a read-only-memory array, while at the same time forming N-channel silicon gate transistors peripheral to the array, comprising the steps of: forming a plurality of N-channel silicon gate memory transistors in a face of a semiconductor body, and at the same time forming a plurality of said peripheral transistors spaced from the array, each of the transistors having a source, a drain and a silicon gate, the memory transistors being in a regular pattern to provide an array of memory cells; programming the array of memory cells by masked ion implant penetrating through the silicon gates of selected ones of the field effect transistors while shielding the peripheral transistors; and thereafter applying patterned metal contacts and interconnections on said face.
Claim 2
Independent Claim
124 words
A method of making a read-only-memory array, while at the same time forming N-channel silicon gate transistors peripheral to the array, comprising the steps of: forming a plurality of N-channel silicon gate memory transistors in a face of a semiconductor body, and at the same time forming a plurality of said peripheral transistors spaced from the array, each of the transistors having a source, a drain and a silicon gate, the memory transistors being in a regular pattern to provide an array of memory cells; programming the array of memory cells by masked ion implant penetrating through the silicon gates of selected ones of the field effect transistors while shielding the peripheral transistors; and thereafter applying patterned metal contacts and interconnections on said face.
Claim 3
Dependent Claim
51 words
A method according to claim 1 wherein a plurality of other transistors and a plurality of contacts and interconnections are formed on said face peripheral to the array, wherein the step of programming uses a mask comprising of a coating of photoresist applied before said contacts and interconnections have been formed.
Claim 4
Dependent Claim
37 words
A method according to claim 2, wherein the field effect transistors and the other transistors are N-channel silicon gate transistors, and the contacts and interconnections are formed by metal deposited uniformly in a thin film and patterned.
Claim 5
Dependent Claim
25 words
A method according to claim 3 wherein the semiconductor body is P-type silicon, the sources and drains are N-type, and the ion implant is P-type.
Claim 6
Independent Claim
126 words
A method a read-only-memory which includes the steps of: forming a plurality of N-channel insulated gate field effect memory transistors in a face of a semiconductor body and at the same time forming a plurality of N-channel insulated gate field effect peripheral transistors in said face, each of the transistors having a source, a drain and a gate, the memory transistors being in a regular pattern to provide an array of memory cells; forming a plurality of metal contacts and inter connections on said face; programming the array of memory cells by ion implant through the gates of selected ones of the memory transistors using a mask applied before said metal contacts and interconnections have been formed, while the gates of the peripheral transistors are shielded.
Claim 7
Independent Claim
126 words
A method a read-only-memory which includes the steps of: forming a plurality of N-channel insulated gate field effect memory transistors in a face of a semiconductor body and at the same time forming a plurality of N-channel insulated gate field effect peripheral transistors in said face, each of the transistors having a source, a drain and a gate, the memory transistors being in a regular pattern to provide an array of memory cells; forming a plurality of metal contacts and inter connections on said face; programming the array of memory cells by ion implant through the gates of selected ones of the memory transistors using a mask applied before said metal contacts and interconnections have been formed, while the gates of the peripheral transistors are shielded.
Claim 8
Dependent Claim
20 words
In a method according to claim 5, the step of programming using a mask comprising a patterned coating of photoresist.
Claim 9
Dependent Claim
38 words
In a method according to claim 5, the field effect transistors and the other transistors being N-channel silicon gate transistors, the semiconductor body being P-type silicon, the sources and drains being N-type, and the ion implant being P-type.
Claim 10
Independent Claim
136 words
A method of making a semiconductor device comprising the steps of: forming a plurality of first circuit elements in a face of a semiconductor body while at the same time forming a plurality of second circuit elements in said face spaced from the first circuit elements; each of the circuit elements having electrodes in the face and a poly silicon control electrode overlying the face: the first circuit elements having a metal interconnection overlying the poly silicon control electrode; the second circuit elements having no metal interconnection over the control electrode; and changing the characteristics of the first circuit elements by ion implant through the poly silicon control electrodes of selected ones of the circuit elements using a mask while shielding the second circuit elements, the ion implant being prior to deposition of the metal interconnection.
Claim 11
Independent Claim
136 words
A method of making a semiconductor device comprising the steps of: forming a plurality of first circuit elements in a face of a semiconductor body while at the same time forming a plurality of second circuit elements in said face spaced from the first circuit elements; each of the circuit elements having electrodes in the face and a poly silicon control electrode overlying the face: the first circuit elements having a metal interconnection overlying the poly silicon control electrode; the second circuit elements having no metal interconnection over the control electrode; and changing the characteristics of the first circuit elements by ion implant through the poly silicon control electrodes of selected ones of the circuit elements using a mask while shielding the second circuit elements, the ion implant being prior to deposition of the metal interconnection.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-10-28 | 1984-04-28 | 1984-10-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-10-28 | 1988-04-28 | 1988-10-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-10-28 | 1992-04-28 | 1992-10-28 | $7700.00 | Window Closed / Lapsed |