US4229474A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Breakage resistant V-grooved <100> silicon substrates
Assignee: Motorola Solutions Inc
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Filing: 1979-05-25
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Granted: 1980-10-21
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Expires: 1999-05-25
Abstract
Abstract Flat and parallel depositions of low pressure chemical vapor deposited (LPCVD) polycrystalline intrinsic silicon are formed on both sides of a wafer of P-I-N <100> substrate of silicon to support the wafer during subsequent polish removal from the top surface. This structurally reinforces the crystal wafer and helps prevent warpage and cracking during subsequent handling.
Inventors
- 👤 Alan L. Harrington
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 09:21
CPC Classifications
H; H10; H10P; H10P52/00; H10P14/00; H10P14/60; H10P50/00; Y; Y10; Y10S; Y10S438/00; Y10S438/977; Y10T; Y10T29/00; Y10T29/49; Y10T29/49789; Y10T29/4979; Y10T428/00; Y10T428/24; Y10T428/24479; Y10T428/24521; Y10T428/24529; Y10T428/2457; Y10T428/24612; Y10T428/2462
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
80 words
A crystalline semiconductive wafer comprising a plurality of V-grooves which are aligned to enable the separation of semiconductive crystals by breaking of the wafer along the V-grooves; a thin polycrystalline intrinsic silicon layer, of approximately 7 to 10 microns in thickness, applied onto the top and bottom sides of the substate; and a thick polycrystalline intrinsic silicon layer, sufficient to fill the grooves, applied over the thin polycrystalline intrinsic silicon layer on the top, the grooved side, of the substrate.
Claim 2
Dependent Claim
80 words
A crystalline semiconductive wafer comprising a plurality of V-grooves which are aligned to enable the separation of semiconductive crystals by breaking of the wafer along the V-grooves; a thin polycrystalline intrinsic silicon layer, of approximately 7 to 10 microns in thickness, applied onto the top and bottom sides of the substate; and a thick polycrystalline intrinsic silicon layer, sufficient to fill the grooves, applied over the thin polycrystalline intrinsic silicon layer on the top, the grooved side, of the substrate.
Claim 3
Dependent Claim
21 words
The structure according to claim 1 in which said thin polycrystalline intrinsic silicon layer completely envelopes both sides of said substrate.
Claim 4
Dependent Claim
36 words
The structure according to claim 1 in which said thick polycrystalline intrinsic silicon layer covers the thin polycrystalline intrinsic silicon layer on the top, V-grooved side of said substrate, thereby filling in completely all the V-grooves.
Claim 5
Dependent Claim
57 words
The structure according to claim 3 in which said thin polycrystalline intrinsic silicon layer is bonded to the bottom side of the substrate and excess polycrystalline intrinsic silicon has been removed by polishing from the top of the substrate, leaving only the V-grooves tilled with a layer of thin polycrystalline intrinsic silicon plus thick polycrystalline intrinsic silicon.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-10-21 | 1984-04-21 | 1984-10-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-10-21 | 1988-04-21 | 1988-10-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-10-21 | 1992-04-21 | 1992-10-21 | $7700.00 | Window Closed / Lapsed |