US4225948A
Expired / Lapsed
US
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Serial access memory device
Assignee: FDS Fast Digital Systems SA
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Filing: 1978-10-06
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Granted: 1980-09-30
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Expires: 1998-10-06
Abstract
Abstract A serial access memory device is disclosed which comprises a random access memory and a synchronous address counter. The address counter is arranged for generating successive address codes which differ by only one bit from each other. The write-enable input signal is continuously effective for writing during the whole recording period. Considerable increase in the recording speed of the memory is obtained.
Inventors
- 👤 Walter H. Schuller
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 22:54
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/04; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/414; G11C11/415
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
185 words
A serail access memory device made in integrated circuit technology and comprising a random access memory including one or more memory units each incorporating an associated address decoder, said random access memory having at least one data input, at least one data output, at least one write-enable input and at least two address inputs, and further comprising a sequential address code generator having a plurality of address outputs and a control input, said control input being connected to a clock signal source and each address output being connected to a corresponding one of the said address inputs of the random access memory, the combination of states of all address outputs at a given time constituting an individual address code determined by the structure of the address code generator and a change from a generated address code to the following one being caused by a clock signal emitted by the said clock signal source, wherein the address code generator is arranged for successively producing binary address codes in which the state of only one of the address outputs changes from one address code to the following.
Claim 2
Dependent Claim
185 words
A serail access memory device made in integrated circuit technology and comprising a random access memory including one or more memory units each incorporating an associated address decoder, said random access memory having at least one data input, at least one data output, at least one write-enable input and at least two address inputs, and further comprising a sequential address code generator having a plurality of address outputs and a control input, said control input being connected to a clock signal source and each address output being connected to a corresponding one of the said address inputs of the random access memory, the combination of states of all address outputs at a given time constituting an individual address code determined by the structure of the address code generator and a change from a generated address code to the following one being caused by a clock signal emitted by the said clock signal source, wherein the address code generator is arranged for successively producing binary address codes in which the state of only one of the address outputs changes from one address code to the following.
Claim 3
Dependent Claim
20 words
A serial access memory in accordance with claim 1, wherein the said address code generator is a cyclic code generator.
Claim 4
Dependent Claim
90 words
A serial access memory device made in integrated circuit technology and comprising a random access memory including one or more memory units each incorporating an associated address decoder, said random access memory having at least one data input, at least one data output, at least one write-enable input and at least two address inputs, and further comprising a synchronous Gray address counter having address outputs which are each connected to a corresponding address input of the random access memory and having a control input connected to a clock signal source.
Claim 5
Dependent Claim
90 words
A serial access memory device made in integrated circuit technology and comprising a random access memory including one or more memory units each incorporating an associated address decoder, said random access memory having at least one data input, at least one data output, at least one write-enable input and at least two address inputs, and further comprising a synchronous Gray address counter having address outputs which are each connected to a corresponding address input of the random access memory and having a control input connected to a clock signal source.
Claim 6
Dependent Claim
25 words
A serial access memory in accordance with any preceding claim, wherein the write-enable input is continuously effective to allow writing during the whole recording period.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-09-30 | 1984-03-31 | 1984-09-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-09-30 | 1988-03-31 | 1988-09-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-09-30 | 1992-03-31 | 1992-09-30 | $7700.00 | Window Closed / Lapsed |