Frequency multiplier for use with CCD comb filter

Claim 2

Frequency multiplier apparatus comprising, in combination: a first amplifying stage including a first transistor having base, emitter and collector electrodes and disposed in a common-emitter amplifier configuration; means for applying input signals of a given frequency to the base electrode of said first transistor; a second transistor having a base, emitter and collector electrodes; means for coupling the collector electrode of said first transistor to the base electrode of said second transistor; a first parallel resonant circuit tuned to said given frequency and coupled between said emitter electrode of said second transistor and a point of reference potential; a signal feedback path coupled between the emitter electrode of said second transistor and the base electrode of said first transistor, said signal feedback path exhibiting a relatively high impedance during zero crossovers of said input signals and a relatively low impedance during intervals intervening said zero crossovers of said input signals; and a narrow-band, frequency selective load circuit for said second transistor coupled to the collector electrode of said second transistor and including a second parallel resonant circuit tuned to a selected harmonic of said given frequency, said selected harmonic frequency corresponding to a given odd integral multiple, different from one, of said given frequency.

Claim 3

Apparatus in accordance with claim 1 wherein said signal feedback path includes: a pair of paralleled, oppositely poled diodes disposed between said emitter electrode of said second transistor and said base electrode of said first transistor.

Claim 4

Apparatus in accordance with claim 1 wherein said signal feedback path includes: a capacitor; and the parallel combination of first and second diodes disposed in parallel with opposite poling; said capacitor being coupled in series with said parallel combination between said emitter electrode of said second transistor and said base electrode of said first transistor.

Claim 5

Apparatus in accordance with claim 3 also including a third parallel resonant circuit tuned to said selected harmonic frequency, and means for capacitively coupling said second parallel resonant circuit to said third parallel resonant circuit.

Claim 6

In a color television receiver including clocked CCD comb filter circuits for separating luminance and chrominance signal components of received composite color television signals, and chrominance signal processing circuits responsive to the chrominance signal component separated by said comb filter circuits; said chrominance signal processing circuits including means for developing reference signals of color subcarrier frequency; clock signal generating means comprising: a first transistor having base, emitter and collector electrodes and disposed in a common-emitter amplifier configuration; means for applying said reference signals to the base electrode of said first transistor; a second transistor having base, emitter and collector electrodes; means for coupling the collector electrode of said first transistor to the base electrode of said second transistor; a first parallel resonant circuit tuned to said color subcarrier frequency and coupled between said emitter electrode of said second transistor and a point of reference potential; a signal feedback path coupled between the emitter electrode of said second transistor and the base electrode of said first transistor, said signal feedback path exhibiting a relatively high impedance during zero crossovers of said reference signals and a relatively low impedance during intervals intervening said zero crossovers of said reference signals; and a frequency selective load circuit for said second transistor coupled to the collector electrode of said second transistor and including a second parallel resonant circuit tuned to the third harmonic of said color subcarrier frequency; means for deriving clock signals, for controlling the clocking of said CCD comb filter circuits, from said frequency selective load circuit.

Claim 7

In a color television receiver including clocked CCD comb filter circuits for separating luminance and chrominance signal components of received composite color television signals, and chrominance signal processing circuits responsive to the chrominance signal component separated by said comb filter circuits; said chrominance signal processing circuits including means for developing reference signals of color subcarrier frequency; clock signal generating means comprising: a first transistor having base, emitter and collector electrodes and disposed in a common-emitter amplifier configuration; means for applying said reference signals to the base electrode of said first transistor; a second transistor having base, emitter and collector electrodes; means for coupling the collector electrode of said first transistor to the base electrode of said second transistor; a first parallel resonant circuit tuned to said color subcarrier frequency and coupled between said emitter electrode of said second transistor and a point of reference potential; a signal feedback path coupled between the emitter electrode of said second transistor and the base electrode of said first transistor, said signal feedback path exhibiting a relatively high impedance during zero crossovers of said reference signals and a relatively low impedance during intervals intervening said zero crossovers of said reference signals; and a frequency selective load circuit for said second transistor coupled to the collector electrode of said second transistor and including a second parallel resonant circuit tuned to the third harmonic of said color subcarrier frequency; means for deriving clock signals, for controlling the clocking of said CCD comb filter circuits, from said frequency selective load circuit.