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US4223326A
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Method and device for reducing the probability of loss of a character in a digital transmission employing biphase coding
Assignee: Individual
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Filing: 1978-04-14
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Granted: 1980-09-16
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Expires: 1998-04-14
Abstract
Abstract A method for reducing the probability of the loss of a character in a digital transmission employing biphase coding which comprises the steps of identifying the bits out-of-code, that is the bits which don't correspond to the two biphase code configurations; complementing the logic value said bits are given by the demodulator, if there is parity error; inhibiting a character not comprising out-of-code bits, but in which parity error occurs or if two or more out-of-code bits are present in the character. The circuit implementing the method comprises shift register means for storing the information bits and control signals identifying the out-of-code bits; parity check means; complementing means for complementing the logic state which are given by the demodulator to the out-of-code bits, said complementing means being conditioned by the simultaneous occurrence of the out-of-code bit and the parity error in a character; logic means for inhibiting the character in presence of parity error alone or of two or more out-of-code bits.
Inventors
- 👤 Paolo D'Amato
- 👤 Mario Cominetti
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 14:59
CPC Classifications
H; H04; H04L; H04L1/00; H04L1/004; H04L27/00; H04L27/18; H04L27/22
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
107 words
A method for reducing the probability of loss of a character provided with a parity (or disparity) bit in biphase coded digital communications, comprising: identifying the bits out-of-code of each character; determining the number of out-of-code bits in the character; checking the parity (or disparity) of the character complementing the logic value of the bits corresponding to the out-of-code bits in the character if the parity (or disparity) check is not met; generating a logic signal denoting a character to be inhibited when the out-of-code bits are more than one or when the parity (or disparity) check is not met and no out-of-code bits have been identified.
Claim 2
Independent Claim
107 words
A method for reducing the probability of loss of a character provided with a parity (or disparity) bit in biphase coded digital communications, comprising: identifying the bits out-of-code of each character; determining the number of out-of-code bits in the character; checking the parity (or disparity) of the character complementing the logic value of the bits corresponding to the out-of-code bits in the character if the parity (or disparity) check is not met; generating a logic signal denoting a character to be inhibited when the out-of-code bits are more than one or when the parity (or disparity) check is not met and no out-of-code bits have been identified.
Claim 3
Independent Claim
86 words
A method for reducing the probability of loss of a character provided with a parity (or disparity) bit in biphase coded digital communications, comprising: identifying the bits out-of-code of each character; checking the parity (or disparity) of the character; complementing the logic value of the bits corresponding to the out-of-code bits in the character if the parity (disparity) check is not met; checking the parity (disparity) of the corrected character and using this new parity signal to inhibit the corrected character whose parity is not met.
Claim 4
Independent Claim
86 words
A method for reducing the probability of loss of a character provided with a parity (or disparity) bit in biphase coded digital communications, comprising: identifying the bits out-of-code of each character; checking the parity (or disparity) of the character; complementing the logic value of the bits corresponding to the out-of-code bits in the character if the parity (disparity) check is not met; checking the parity (disparity) of the corrected character and using this new parity signal to inhibit the corrected character whose parity is not met.
Claim 5
Independent Claim
162 words
A device for reducing the probability of loss of a character provided with a parity (or disparity) bit in biphase coded digital communications, the device comprising: means for receiving the biphase signal and identifying the bits out-of-code of each character; means responsive to said identifying means for determining the number of out-of-code bits in the character; means for receiving the biphase signal and checking the parity (disparity) of the character; means responsive to the output of the identifying means, the checking means and the determining means for complementing the logic value of the bits corresponding to the out-of-code bits of the character if the parity (disparity) check is not met; means also responsive to the output of the identifying means, the checking means and the determining means for generating a logic signal denoting a character to be inhibited when the out-of-code bits are more than one or when the parity (disparity) check is not met and no out-of-code bits have been identified.
Claim 6
Independent Claim
162 words
A device for reducing the probability of loss of a character provided with a parity (or disparity) bit in biphase coded digital communications, the device comprising: means for receiving the biphase signal and identifying the bits out-of-code of each character; means responsive to said identifying means for determining the number of out-of-code bits in the character; means for receiving the biphase signal and checking the parity (disparity) of the character; means responsive to the output of the identifying means, the checking means and the determining means for complementing the logic value of the bits corresponding to the out-of-code bits of the character if the parity (disparity) check is not met; means also responsive to the output of the identifying means, the checking means and the determining means for generating a logic signal denoting a character to be inhibited when the out-of-code bits are more than one or when the parity (disparity) check is not met and no out-of-code bits have been identified.
Claim 7
Independent Claim
120 words
A device for reducing the probability of loss of a character provided with a parity (or disparity) bit in biphase coded digital communications, the device comprising: means for receiving the biphase signal and identifying the bits out-of-code of each character means for receiving the biphase signal and checking the parity (disparity) of the character; means responsive to said identifying means and said checking means for complementing the logic value of the bits corresponding to the out-of-code bits in the character if the parity (disparity) check is not met; means responsive to said last mentioned means for checking the parity (disparity) of the corrected character for using this new parity signal to inhibit the corrected character whose parity is not met.
Claim 8
Independent Claim
120 words
A device for reducing the probability of loss of a character provided with a parity (or disparity) bit in biphase coded digital communications, the device comprising: means for receiving the biphase signal and identifying the bits out-of-code of each character means for receiving the biphase signal and checking the parity (disparity) of the character; means responsive to said identifying means and said checking means for complementing the logic value of the bits corresponding to the out-of-code bits in the character if the parity (disparity) check is not met; means responsive to said last mentioned means for checking the parity (disparity) of the corrected character for using this new parity signal to inhibit the corrected character whose parity is not met.
Claim 9
Independent Claim
146 words
A device for use with a biphase demodulator, for reducing the probability of loss of a character provided with a parity (disparity) bit in biphase coded digital communications, said device comprising at least two shift registers which receive the character and the logic values of the character bits and a signal identifying the out-of-code bits of the character; a circuit responsive to said registers for checking the parity (disparity) in each character; a plurality of complementing circuits connected to said register which complement the logic value assigned by the modulator to the out-of-code bits, said circuits being conditioned by the simultaneous presence of the out-of-code bits and of the parity error in the character; a validation circuit coupled to said circuits which causes said character to be neglected if the parity error occurs alone or it there are two or more out-of-code bits in the character.
Claim 10
Independent Claim
146 words
A device for use with a biphase demodulator, for reducing the probability of loss of a character provided with a parity (disparity) bit in biphase coded digital communications, said device comprising at least two shift registers which receive the character and the logic values of the character bits and a signal identifying the out-of-code bits of the character; a circuit responsive to said registers for checking the parity (disparity) in each character; a plurality of complementing circuits connected to said register which complement the logic value assigned by the modulator to the out-of-code bits, said circuits being conditioned by the simultaneous presence of the out-of-code bits and of the parity error in the character; a validation circuit coupled to said circuits which causes said character to be neglected if the parity error occurs alone or it there are two or more out-of-code bits in the character.
Claim 11
Independent Claim
132 words
A device for use with a biphase demodulator, for reducing the probability of loss of a character provided with a parity (disparity) bit in biphase coded digital communications, said device comprising at least two shift registers which receive the character and store the logic values of the character bits and a identifying the out-of-code bits, a circuit responsive to said registers for checking the parity (disparity) in each character, a pluraity of complementing circuits connected to said registers which complement the logic state assigned by the demodulator to the out-of-code bits, said complementing circuits being conditioned by the simultaneous occurrence of the out-of-code bits and the parity error in the character, and a second parity check circuit coupled to said complementing circuit for neglecting the corrected character whose parity is not met.
Claim 12
Independent Claim
132 words
A device for use with a biphase demodulator, for reducing the probability of loss of a character provided with a parity (disparity) bit in biphase coded digital communications, said device comprising at least two shift registers which receive the character and store the logic values of the character bits and a identifying the out-of-code bits, a circuit responsive to said registers for checking the parity (disparity) in each character, a pluraity of complementing circuits connected to said registers which complement the logic state assigned by the demodulator to the out-of-code bits, said complementing circuits being conditioned by the simultaneous occurrence of the out-of-code bits and the parity error in the character, and a second parity check circuit coupled to said complementing circuit for neglecting the corrected character whose parity is not met.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-09-16 | 1984-03-17 | 1984-09-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-09-16 | 1988-03-17 | 1988-09-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-09-16 | 1992-03-17 | 1992-09-16 | $7700.00 | Window Closed / Lapsed |