Thyristor having low on-state voltage with low areal doping emitter region

Claim 2

A thyristor comprising: a semiconductor substrate consisting of a first semiconductor layer of one conductivity type, a second semiconductor layer of the other conductivity type contiguous to said first semiconductor layer and defining a first PN junction between it and said first semiconductor layer, a third semiconductor layer of said one conductivity type contiguous to said second semiconductor layer and defining a second PN junction between it and said second semiconductor layer, and a fourth semiconductor layer of said the other conductivity type contiguous to said third semiconductor layer and defining a third PN junction between it and said third semiconductor layer, the regions of said second and third semiconductor layers having a higher resistivity than those of said first and fourth semiconductor layers, the sum of the thicknesses of said second and third semiconductor layers in a direction from said first layer toward said fourth layer being less than 400μ, the amount of impurities per unit area of said first semiconductor layer being less than that of said fourth semiconductor layer and selected to be less than 2×10 13 atoms/cm 2 but more than a minimum required for the thyristor operation; a first main electrode connected electrically to the surface of said first semiconductor layer; a second main electrode in ohmic contact with the surface of said fourth semiconductor layer; and the regions of said semiconductor substrate between said first and second main electrodes being adapted to be triggered to switchover from a non-conductive state to a conductive state.

Claim 3

A thyristor as claimed in claim 1, wherein the triggering is effected electrically.

Claim 4

A thyristor as claimed in claim 1, wherein the triggering is effected optically.

Claim 5

A thyristor comprising: a semiconductor substrate having a first major surface and a second major surface opposite to each other and consisting, between said first and second major surfaces, of a first semiconductor layer of one conductivity type, a second semiconductor layer of the other conductivity type contiguous to said first semiconductor layer and defining a first PN junction between it and said first semiconductor layer, a third semiconductor layer of said one conductivity type contiguous to said second semiconductor layer and defining a second PN junction between it and said second semiconductor layer, and a fourth semiconductor layer of said the other conductivity type contiguous to said third semiconductor layer and defining a third PN junction between it and said third semiconductor layer, said first major surface being provided at least by the exposed surface of said first semiconductor layer and said second major surface being provided at least by the exposed surface of said fourth semiconductor layer, the regions of said second and third semiconductor layers having a higher resistivity than those of said first and fourth semiconductor layers, the sum of the thicknesses of said second and third semiconductor layers in a direction from said first layer toward said fourth layer being less than 400μ, the amount of impurities per unit area of said first semiconductor layer being less than that of said fourth semiconductor layer and selected to be less than 2×10 13 atoms/cm 2 but more than a minimum required for thyristor operation; a first main electrode connected electrically to the surface of said first semiconductor layer; a second main electrode in ohmic contact with at least the exposed surface of said fourth semiconductor layer at said second major surface; and the regions of said semiconductor substrate between said first and second main electrodes being adapted to be triggered to switchover from a non-conductive state to a conductive state.

Claim 6

A thyristor comprising: a semiconductor substrate having a first major surface and a second major surface opposite to each other and consisting, between said first and second major surfaces, of a first semiconductor layer of one conductivity type, a second semiconductor layer of the other conductivity type contiguous to said first semiconductor layer and defining a first PN junction between it and said first semiconductor layer, a third semiconductor layer of said one conductivity type contiguous to said second semiconductor layer and defining a second PN junction between it and said second semiconductor layer, and a fourth semiconductor layer of said the other conductivity type contiguous to said third semiconductor layer and defining a third PN junction between it and said third semiconductor layer, said first major surface being provided at least by the exposed surface of said first semiconductor layer and said second major surface being provided at least by the exposed surface of said fourth semiconductor layer, the regions of said second and third semiconductor layers having a higher resistivity than those of said first and fourth semiconductor layers, the sum of the thicknesses of said second and third semiconductor layers in a direction from said first layer toward said fourth layer being less than 400μ, the amount of impurities per unit area of said first semiconductor layer being less than that of said fourth semiconductor layer and selected to be less than 2×10 13 atoms/cm 2 but more than a minimum required for thyristor operation; a first main electrode connected electrically to the surface of said first semiconductor layer; a second main electrode in ohmic contact with at least the exposed surface of said fourth semiconductor layer at said second major surface; and the regions of said semiconductor substrate between said first and second main electrodes being adapted to be triggered to switchover from a non-conductive state to a conductive state.

Claim 7

A thyristor as claimed in claim 4, wherein the triggering is effected electrically.

Claim 8

A thyristor as claimed in claim 4, wherein the triggering is effected optically.

Claim 9

A thyristor as claimed in claim 4, comprises a polycrystalline semiconductor layer containing an impurity of said one conductivity type formed on said first semiconductor layer, said first semiconductor layer being formed by diffusion of said impurity from said polycrystalline semiconductor layer.

Claim 10

A thyristor as claimed in claim 7, wherein said first main electrode is in ohmic contact with the surface of said polycrystalline semiconductor layer and is provided by a metal containing essentially a metal selected from the group consisting of chromium, molybdenum and tungsten.

Claim 11

A thyristor as claimed in claim 4, wherein said one conductivity type is the P-type, and said the other conductivity type is the N-type.

Claim 12

A thyristor as claimed in claim 4, wherein said one conductivity type is the N-type, and said the other conductivity type is the P-type.

Claim 13

A thyristor as claimed in claim 7, wherein said third semiconductor layer is exposed at said second major surface, and said second main electrode is in ohmic contact with said third semiconductor layer.