US4217601A — Non-volatile memory devices fabricated from grade…

Claim 1

Independent Claim 102 words

A metal-insulator-metal or metal-insulator-semiconductor structure, wherein the band gap of the insulator layer at its first interface only is reduced to provide an injection region where holes or electrons depending on voltage bias, can be injected into the insulator under low to moderate electrical field conditions from the contact at this interface while, simultaneously, electron or hole injection from said insulator's second interface is blocked due to the large insulator band gap near said second interface, the improvement being a charge trapping layer embedded in said insulator near its second interface for capturing and storing injected electrons or holes with high efficiency.

Claim 2

Dependent Claim 102 words

A metal-insulator-metal or metal-insulator-semiconductor structure, wherein the band gap of the insulator layer at its first interface only is reduced to provide an injection region where holes or electrons depending on voltage bias, can be injected into the insulator under low to moderate electrical field conditions from the contact at this interface while, simultaneously, electron or hole injection from said insulator's second interface is blocked due to the large insulator band gap near said second interface, the improvement being a charge trapping layer embedded in said insulator near its second interface for capturing and storing injected electrons or holes with high efficiency.

Claim 3

Dependent Claim 57 words

The device of claim 1 comprising a silicon substrate having thereon a relatively thick insulator having embedded therein a layer of impurity atoms proximate to said insulator's second interface at said substrate and said thick insulator having a decreasing band gap in the vicinity of its first interface, said decreasing band gap being produced by ion implantation.

Claim 4

Dependent Claim 62 words

The device of claim 1 comprising a silicon substrate having a first relatively thick oxide insulator thereon said insulator having embedded therein a layer of impurity atoms proximate to its interface with said substrate and over which is deposited a relatively thin layer of Si 3 N 4 and a metal or semiconductor contact on the deposited Si 3 N 4 layer.

Claim 5

Dependent Claim 79 words

The device of claim 1 comprising a silicon substrate having a first relatively thick oxide insulator thereon said insulator having embedded therein a layer of impurity atoms proximate to said its interface with said substrate, and over which is deposited a plurality of relatively thin pyrolytic or plasma oxide layers, each successively deposited pyrolytic or plasma oxide layer containing an increasing excess silicon content, and a metal or semiconductor contact on the last pyrolytic or plasma deposited oxide layer.

Claim 6

Dependent Claim 44 words

A stepped insulator metal-silicon dioxide-silicon SIMOS FET structure having an injection region adjacent to the gate electrode, said injection region comprising a thin stepped band gap insulator adjacent to a relatively thick silicon dioxide insulator layer having embedded therein a layer of impurity atoms.

Claim 7

Dependent Claim 44 words

A stepped insulator metal-silicon dioxide-silicon SIMOS FET structure having an injection region adjacent to the gate electrode, said injection region comprising a thin stepped band gap insulator adjacent to a relatively thick silicon dioxide insulator layer having embedded therein a layer of impurity atoms.

Claim 8

Dependent Claim 38 words

A stepped insulator metal-silicon dioxide-silicon SIMOS FET structure of claim 5 wherein the gate structure comprises a relatively thick oxide on a silicon substrate and a relatively thin layer of Si 3 N 4 formed over the oxide.

Claim 9

Dependent Claim 46 words

An improved graded oxide metal-silicon dioxide silicon GIMOS FET structure having an injection region adjacent to the gate electrode, said injection region comprising a thin graded band gap, said improvement being a layer of impurity atoms embedded in an oxide layer adjacent to the silicon substrate.

Claim 10

Dependent Claim 46 words

An improved graded oxide metal-silicon dioxide silicon GIMOS FET structure having an injection region adjacent to the gate electrode, said injection region comprising a thin graded band gap, said improvement being a layer of impurity atoms embedded in an oxide layer adjacent to the silicon substrate.

Claim 11

Dependent Claim 61 words

An improved GIMOS FET structure as in claim 7 wherein the structure comprises a relatively thick oxide on a silicon substrate, having embedded in said oxide a layer of impurity atoms and a plurality of relatively thin pyrolytic or plasma deposited oxide layers formed over the oxide, each successive pyrolytic or plasma deposited oxide layer containing an increasing excess silicon content.

Claim 12

Dependent Claim 142 words

In a MOS FET device for performing a memory function said device being of the type comprising a silicon substrate having source and drain regions formed therein and an insulated gate structure formed between said source and drain regions, and wherein the band gap of the insulator of the insulated gate structure is reduced near the gate electrical contact interface to provide an injection region wherein holes or electrons depending on voltage bias, can be injected into the insulator under low to moderate electric field conditions from the gate electrical contact while simultaneously, electron or hole injection from the substrate interface is blocked due to the large insulator band gap at this interface, the improvement being a layer of impurity atoms embedded in said gate oxide proximate to the oxide-silicon interface for capturing and storing injected electrons or holes with high efficiency.

Claim 13

Dependent Claim 142 words

In a MOS FET device for performing a memory function said device being of the type comprising a silicon substrate having source and drain regions formed therein and an insulated gate structure formed between said source and drain regions, and wherein the band gap of the insulator of the insulated gate structure is reduced near the gate electrical contact interface to provide an injection region wherein holes or electrons depending on voltage bias, can be injected into the insulator under low to moderate electric field conditions from the gate electrical contact while simultaneously, electron or hole injection from the substrate interface is blocked due to the large insulator band gap at this interface, the improvement being a layer of impurity atoms embedded in said gate oxide proximate to the oxide-silicon interface for capturing and storing injected electrons or holes with high efficiency.

Claim 14

Dependent Claim 40 words

The MOS FET device of claim 9 wherein the insulator comprises an oxide having a thin layer of Si 3 N 4 deposited thereon to provide a low band gap insulator in the vicinity of the gate electrical contact interface.

Claim 15

Dependent Claim 36 words

The MOS FET device of claim 9 wherein the insulator comprises an oxide having a decreasing band gap in the vicinity of the gate electrical contact interface, said decreasing band gap being produced by ion implantation.

Claim 16

Dependent Claim 43 words

The MOSFET device of claim 9 wherein the insulator comprises a first relatively thick oxide layer over which is deposited a plurality of relatively thin pyrolytic or plasma oxide layers, each successively deposited pyrolytic or plasma oxide layers containing an increasing silicon content.

Claim 17

Dependent Claim 104 words

A metal-insulator-metal or metal-insulator-semiconductor structure, wherein the band gap of the insulator layer at its first interface only is reduced to provide an injection region where holes or electrons depending on voltage bias, can be injected into the insulator under low to moderate electrical field conditions from the contact at this interface while, simultaneously, electron or hole injection from said insulator's second interface is blocked due to the large insulator band gap near said second interface, the improvement being a floating polycrystalline silicon charge storage layer in said insulator near its second interface for capturing and storing injected electrons or holes with high efficiency.

Claim 18

Dependent Claim 104 words

A metal-insulator-metal or metal-insulator-semiconductor structure, wherein the band gap of the insulator layer at its first interface only is reduced to provide an injection region where holes or electrons depending on voltage bias, can be injected into the insulator under low to moderate electrical field conditions from the contact at this interface while, simultaneously, electron or hole injection from said insulator's second interface is blocked due to the large insulator band gap near said second interface, the improvement being a floating polycrystalline silicon charge storage layer in said insulator near its second interface for capturing and storing injected electrons or holes with high efficiency.

Claim 19

Dependent Claim 20 words

The metal-insulator-metal or metal-insulator-semiconductor structure of claim 13 wherein said injection regions is separate and apart from said gate region.

Claim 20

Dependent Claim 45 words

A stepped insulator metal-silicon dioxide-silicon SIMOS FET structure having an injection region adjacent to the gate electrode, said injection region comprising a thin stepped band gap insulator, adjacent to a relatively thick silicon dioxide insulator layer having a floating polycrystalline silicon charge storage layer therein.

Claim 21

Dependent Claim 45 words

A stepped insulator metal-silicon dioxide-silicon SIMOS FET structure having an injection region adjacent to the gate electrode, said injection region comprising a thin stepped band gap insulator, adjacent to a relatively thick silicon dioxide insulator layer having a floating polycrystalline silicon charge storage layer therein.

Claim 22

Dependent Claim 21 words

A stepped insulator metal-silicon dioxide-silicon SIMOS FET structure of claim 15 wherein said injection regions are separate from said gate region.

Claim 23

Dependent Claim 48 words

An improved graded oxide metal-silicon dioxide silicon GIMOS FET structure having an injection region adjacent to the gate electrode, said injection region comprising a thin graded band gap insulator, said improvement being a floating polycrystalline silicon charge storage layer in an oxide layer adjacent to the silicon substrate.

Claim 24

Dependent Claim 48 words

An improved graded oxide metal-silicon dioxide silicon GIMOS FET structure having an injection region adjacent to the gate electrode, said injection region comprising a thin graded band gap insulator, said improvement being a floating polycrystalline silicon charge storage layer in an oxide layer adjacent to the silicon substrate.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1983-08-12	1984-02-11	1984-08-12	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1987-08-12	1988-02-11	1988-08-12	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1991-08-12	1992-02-11	1992-08-12	$7700.00	Window Closed / Lapsed

Non-volatile memory devices fabricated from graded or stepped energy band gap insulator MIM or MIS structure

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