Patent US4215416A successfully refreshed from Google Patents.
US4215416A
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US
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Integrated multiplier-accumulator circuit with preloadable accumulator register
Assignee: Fairchild Semiconductor Corp
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Filing: 1978-03-22
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Granted: 1980-07-29
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Expires: 1998-03-22
Abstract
Abstract An integrated circuit having a preloadable accumulator register for accumulating the arithmetic sum of a succession of multiplier products therein. The circuit includes preload control logic for selecting data for storage in the accumulator register either from input terminals, from a summing circuit which receives current product data and accumulated product data, or from the accumulator register itself. Depending upon the conditions of a preload control signal and field selection signals, the preload control logic can either preload selected fields of the register with input data, leaving unselected fields intact, or can store current or accumulated product data in the register.
Inventors
- 👤 John J. Muramatsu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 06:37
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/52; G06F7/523; G06F7/53; G06F7/5306; G06F7/5312; G06F7/544; G06F7/5443; G06F7/499; G06F7/49942; G06F7/49947
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
192 words
An integrated digital multiplier-accumulator circuit comprising: a digital multiplier circuit; a digital summing circuit having first and second input circuits, said first input circuit being connected to receive data from said multiplier circuit; an accumulator register having input terminals and output terminals; accumulator control means, responsive to accumulation control signals, for selectively transmitting data from said output terminals of said accumulator register back to said second input circuit of said summing circuit; a set of data terminals having the dual purpose of data output from said accumulator register and data input to said accumulator register; buffer means coupled to said output terminals of said accumulator register and to said set of data terminals, said buffer means being switchable to a high-impedance state to isolate said accumulator register from said data terminals; and preload control means having one output circuit connected to said input terminals of said accumulator register, and three input circuits connected, respectively, to said output terminals of said accumulator register, to said summing circuit, and to said set of data terminals, said preload control means being controllable to select input data from a selected one of its three input circuits.
Claim 2
Dependent Claim
192 words
An integrated digital multiplier-accumulator circuit comprising: a digital multiplier circuit; a digital summing circuit having first and second input circuits, said first input circuit being connected to receive data from said multiplier circuit; an accumulator register having input terminals and output terminals; accumulator control means, responsive to accumulation control signals, for selectively transmitting data from said output terminals of said accumulator register back to said second input circuit of said summing circuit; a set of data terminals having the dual purpose of data output from said accumulator register and data input to said accumulator register; buffer means coupled to said output terminals of said accumulator register and to said set of data terminals, said buffer means being switchable to a high-impedance state to isolate said accumulator register from said data terminals; and preload control means having one output circuit connected to said input terminals of said accumulator register, and three input circuits connected, respectively, to said output terminals of said accumulator register, to said summing circuit, and to said set of data terminals, said preload control means being controllable to select input data from a selected one of its three input circuits.
Claim 3
Dependent Claim
167 words
An integrated digital multiplier-accumulator circuit as set forth in claim 1, wherein: said preload control means is responsive to a first state of a preload control signal to select input data from said summing circuit; said preload control means is responsive to a second state of said preload control signal and to a first state of a field selection signal, to select input data from said data terminals and to switch said buffer means to the high-impedance state; said preload control means is responsive to the second state of said preload control signal and to a second state of said field selection signal, to select input data from said output terminals of said said accumulator register and to switch said buffer means out of the high-impendance state; and a field selection signal of said first state is applied to selected fields of said preload control means, to preload input data into corresponding selected fields of said accumulator register, while leaving unselected fields of said accumulator register intact.
Claim 4
Dependent Claim
64 words
An integrated digital multiplier-accumulator circuit as set forth in claims 1 or 2, wherein said accumulator control means includes: first gating means, for selectively gating data from said output terminals of said accumulator register to said second input circuit of said summing circuit; and second gating means, for selectively inverting data from said output terminals, to provide for its subtraction in said summing circuit.
Claim 5
Dependent Claim
119 words
An integrated digital multiplier-accumulator circuit as set forth in claim 1, wherein said preload control means includes: first gating means operable to select input data from said summing circuit; second gating means operable to select input data from said set of data terminals; third gating means operable to select input data from said accumulator register; fourth gating means, for transmitting data selected by one of said first, second and third gating means to said accumulator register input terminals; and fifth gating means for switching said buffer means to its high-impedance state when said second switching means is enabled to select input data from said set of data terminals, or when a field selection signal is in a particular state.
Claim 6
Dependent Claim
138 words
An integrated digital multiplier-accumulator circuit as set forth in claim 1, wherein: control of said preload control means is effected by the combined states of a preload control signal and at least one field selection signal; said preload control signal has a first state to provide selection of input data from said summing circuit and a second state to provide selection of input data from selected fields of said set of data terminals; and said preload control means includes means responsive to said field selection signal, to control the impedance state of said buffer means when said preload control signal is in its first state, and means also responsive to said field selection signal, to control which fields are selected for preloading of data from said data terminals when said preload control signal is in its second state.
Claim 7
Dependent Claim
119 words
An integrated digital multiplier-accumulator circuit as set forth in claim 1, wherein said preload control means includes: means responsive to a first state of a preload control signal to effect selection of input data from said summing circuit; means responsive to a second state of the preload control signal, to effect selection of input data from said set of data terminals; and means responsive to a field selection signal, for selecting fields of said accumulator register to be preloaded with input data when the preload control signal is in the second state, and for selecting fields of said accumulator register to be isolated from said set of data terminals when the preload control signal is in the first state.
Claim 8
Dependent Claim
178 words
An integrated digital multiplier-accumulator circuit comprising: a digital multiplier circuit; an accumulator register having input terminals and output terminals; a set of data terminals for the application of externally supplied input data to said accumulator register; a summing circuit connected to receive input signals from said multiplier circuit and from said accumulator register and to provide an output signal indicative of the sum of the input signals; and preload control means, including means for selecting between data derived from said summing circuit and data supplied through said data terminals, and transmitting such selected data to said accumulator register, said preload control means being connected to receive inputs from said data terminals and from said summing circuit output signal, and to provide outputs to said accumulator register; and wherein said preload control means effects preloading of said accumulator register with selected data when said preload control means selects data supplied through said data terminals, and effects accumulation of data from said multiplier circuit in said accumulator register, when said preload control means selects data derived from said summing circuit.
Claim 9
Dependent Claim
178 words
An integrated digital multiplier-accumulator circuit comprising: a digital multiplier circuit; an accumulator register having input terminals and output terminals; a set of data terminals for the application of externally supplied input data to said accumulator register; a summing circuit connected to receive input signals from said multiplier circuit and from said accumulator register and to provide an output signal indicative of the sum of the input signals; and preload control means, including means for selecting between data derived from said summing circuit and data supplied through said data terminals, and transmitting such selected data to said accumulator register, said preload control means being connected to receive inputs from said data terminals and from said summing circuit output signal, and to provide outputs to said accumulator register; and wherein said preload control means effects preloading of said accumulator register with selected data when said preload control means selects data supplied through said data terminals, and effects accumulation of data from said multiplier circuit in said accumulator register, when said preload control means selects data derived from said summing circuit.
Claim 10
Dependent Claim
77 words
An integrated digital multiplier-accumulator circuit as set forth in claim 7, wherein: said data terminals also serve as output terminals for said accumulator register; and said multiplier-accumulator circuit further includes buffer means coupling said output terminals of said accumulator register to said data terminals, said buffer means being switchable to a high-impedance state to allow input of data from said data terminals, and to a low-impedance state to allow said data terminals to serve as output terminals.
Claim 11
Dependent Claim
140 words
An integrated digital multiplier-accumulator circuit as set forth in claims 7 or 8, wherein: said preload control means further includes means for selecting data from said output terminals of said accumulator register for input to said accumulator register; said preload control means is responsive to the state of a preload control signal and the state of a field selection signal, for selecting accumulator register input data from said summing circuit, said data terminals, and said accumulator register; said preload control means has a plurality of separate stages corresponding to digital stages of said accumulator register; and wherein said field selection signal is applied to selected stages of said preload control means, to enable preloading of data into only selected fields of said accumulator register, unselected fields of said register remaining intact by recirculation of data through said preload control means.
References Cited (Backward Citations)
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Cited
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Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-07-29 | 1984-01-28 | 1984-07-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-07-29 | 1988-01-28 | 1988-07-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-07-29 | 1992-01-28 | 1992-07-29 | $7700.00 | Window Closed / Lapsed |