US4213178A — Input/output command timing mechanism

Claim 1

Independent Claim 400 words

A circuit for overseeing input/output activity in a digital computing system comprising a processing unit, digital storage, and a plurality of input/output operation units, the input/output operation units being connected to an input/output channel bus for communication with the processing unit and storage, the circuit comprising: (a) a memory array having a plurality of storage locations capable of storing a plurality of subchannel status words, each subchannel status word corresponding to an input/output operation unit and encoding control information for an input/output operation by the input/output operation unit, each subchannel status word having a timing monitor field including a current-count subfield, a count-limit subfield, and a command-in-progress subfield; (b) load-timing-control-data circuit means connected to the central-processing unit and to the memory array for loading subchannel status words selected by the central processing unit with timing control data in response to control signals from the central processing unit, the count-limit subfield being loaded with data from the central processing unit encoding a count-limit number, the command-in-progress bit position being set to a state indicating that an input/output operation had been requested of the corresponding input/output operation unit, and the current-count subfield being cleared to a state encoding the number zero; (c) an interval timer for emitting clock signals at timed intervals; (d) count-incrementer circuit means connected to the interval timer and to the memory array for repetitively incrementing numbers encoded in the current-count subfields of subchannel status words for which the command-in-progress subfield indicates that an input/output operation has been requested, the repetitive incrementing being carried out in response to clock signals from the interval timer so that the number encoded in the current-count subfield of a particular subchannel status word measures the approximate time from the most recent request to the corresponding input/output operation unit for an input/output operation; (e) comparator-search circuit means for testing each subchannel status word for which the command-in-progress bit position indicates an input/output operation request has been made by comparing the number encoded in the current-count subfield with the number encoded in the count-limit subfield and for generating a response overdue signal if the count limit has been exceeded; and (f) command-end circuit means connected to the input/output channel bus and to the memory array for accessing subchannel status words identified over the input/output channel bus to clear the command-in-progress subfield to a state indicating that the request for an input/output operation has been satisfied.

Claim 2

Dependent Claim 400 words

A circuit for overseeing input/output activity in a digital computing system comprising a processing unit, digital storage, and a plurality of input/output operation units, the input/output operation units being connected to an input/output channel bus for communication with the processing unit and storage, the circuit comprising: (a) a memory array having a plurality of storage locations capable of storing a plurality of subchannel status words, each subchannel status word corresponding to an input/output operation unit and encoding control information for an input/output operation by the input/output operation unit, each subchannel status word having a timing monitor field including a current-count subfield, a count-limit subfield, and a command-in-progress subfield; (b) load-timing-control-data circuit means connected to the central-processing unit and to the memory array for loading subchannel status words selected by the central processing unit with timing control data in response to control signals from the central processing unit, the count-limit subfield being loaded with data from the central processing unit encoding a count-limit number, the command-in-progress bit position being set to a state indicating that an input/output operation had been requested of the corresponding input/output operation unit, and the current-count subfield being cleared to a state encoding the number zero; (c) an interval timer for emitting clock signals at timed intervals; (d) count-incrementer circuit means connected to the interval timer and to the memory array for repetitively incrementing numbers encoded in the current-count subfields of subchannel status words for which the command-in-progress subfield indicates that an input/output operation has been requested, the repetitive incrementing being carried out in response to clock signals from the interval timer so that the number encoded in the current-count subfield of a particular subchannel status word measures the approximate time from the most recent request to the corresponding input/output operation unit for an input/output operation; (e) comparator-search circuit means for testing each subchannel status word for which the command-in-progress bit position indicates an input/output operation request has been made by comparing the number encoded in the current-count subfield with the number encoded in the count-limit subfield and for generating a response overdue signal if the count limit has been exceeded; and (f) command-end circuit means connected to the input/output channel bus and to the memory array for accessing subchannel status words identified over the input/output channel bus to clear the command-in-progress subfield to a state indicating that the request for an input/output operation has been satisfied.

Claim 3

Dependent Claim 131 words

The circuit according to claim 1 in which the count-incrementer circuit means includes: (d.1) an address counter for sequentially generating the addresses of the subchannel status words in the memory array: (d.2) read-array circuit means connected to the address counter and to the memory array for fetching at least the current-count subfield and the count-limit subfield of a subchannel status word whose address has been generated by the address counter; (d.3) an incrementer connected to the read-array circuit means for incrementing the number encoded in the current-count subfield of the subchannel status word fetched from the memory array; and (d.4) write-array circuit means connected to the incrementer and to the memory array for writing the encoded incremented number into the current-count subfield of the subchannel-status-word location addressed by the address counter.

Claim 4

Dependent Claim 61 words

The circuit according to claim 2 in which the comparator-search circuit means includes a comparator for signalling when a number of a first input equals a number at a second input, the first input being connected to the incremented number output of the incrementer and the second input being connected to a fetch count-limit subfield output of the read-array circuit means.

Claim 5

Dependent Claim 66 words

The circuit according to claim 3 in which the timing monitor field of each subchannel status word further includes a command-timing-enabled subfield defining a clear state and a counter-enabled state, and the count-incrementer circuit means further includes: (d.5) clear-incrementer circuit means connected to the read-array circuit means and to the incrementer for clearing the incrementer in response to a clear state in the command-timing enabled subfield.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1983-07-15	1984-01-14	1984-07-15	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1987-07-15	1988-01-14	1988-07-15	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1991-07-15	1992-01-14	1992-07-15	$7700.00	Window Closed / Lapsed

Input/output command timing mechanism

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