Redundant operation of counter modules

Claim 2

In a system having a plurality of multistage counters for operation in parallel to provide a counter output code representative of a plurality of states, including a state representing a count of zero, for continued operation of said system in the event of failure of any one counter, the combination comprising separate detecting means connected to each counter for detecting the zero state thereof, thus providing a number of detecting means equal to the number of counters, one detecting means for each counter, separate AC coupling means connected to each of said detecting means for setting to the zero state all others of said counters upon detecting said zero state in any one counter, two single set of output terminals for all stages of said counters, one terminal for each stage of one counter shared by corresponding stages of all other counters, and unidirectional AC coupling means coupling each terminal of said set of output terminals to corresponding stages of said counters, whereby continued operation of any one counter will continue to provide a counter output code at said set of output terminals.

Claim 3

The combination of claim 1 wherein said unidirectional AC coupling means is comprised of a circuit for each stage of each counter having a capacitor in series with a diode coupling each output terminal to a stage of a counter, and further comprised of a separate plurality of load resistors for each stage, said load resistors for each stage being connected in parallel between an output terminal and circuit ground.

Claim 4

The combination of claim 1 wherein said separate AC coupling means connected to each of said detecting means is each comprised of a plurality of capacitors connected in series.

Claim 5

The combination of claim 1 wherein each stage of said counters is comprised of a plurality of flip-flops operated in parallel to provide continued operation of said system in the event of failure of any one of said flip-flops, each one of said flip-flops having one output terminal AC coupled to all others of said flip-flops operated in parallel to set all others to a predetermined state when said one is changed to said predetermined state, and unidirectional AC coupling means within the stage for coupling a corresponding output terminal of each of said flip-flops operated in parallel to a common one of said set of output terminals for said counters.

Claim 6

The combination of claim 4 wherein said unidirectional AC coupling means within each stage is comprised of a circuit for each flip-flop having a capacitor in series with a diode, and further comprised of a plurality of load resistors connected in parallel between said common one of said set of output terminals for said counters and circuit ground.

Claim 7

The combination of claim 4 wherein the one output terminal of each flip-flop AC coupled to all others of said flip-flops is so coupled by a plurality of capacitors connected in series.

Claim 8

The combination of claim 1 including a source of clock pulses for all of said counters operated in parallel, said source of clock pulses being comprised of a plurality of clock pulse generators operated in parallel, each having an output terminal for delivering clock pulses to a common output terminal, and means for continually forcing frequency and phase synchronization between said clock pulse generators so that if one clock pulse source fails, the frequency and phase of clock pulses delivered to said common output terminal are unaffected.

Claim 9

The combination of claim 7 wherein each of said plurality of clock pulse generators has a unidirectional AC coupling means for coupling the output terminal thereof to said common junction.

Claim 10

The combination of claim 8 wherein each of said unidirectional AC coupling means for coupling the output terminals of said clock pulse generators to said common junction is comprised of a circuit having a capacitor and a diode connected in series and a plurality of load resistors connected in parallel between said common junction and circuit ground.

Claim 11

The combination of claim 7 wherein each of said plurality of clock pulse generators is comprised of a squarewave generator having an input terminal and an output terminal, and having an RC feedback circuit connected from said generator output terminal to said generator input terminal for continued oscillation, and resistance means connecting the input terminals of all squarewave generators to one another.

Claim 12

The combination of claim 10 wherein said resistance means is comprised of a plurality of resistors connected in parallel from the input terminal of one squarewave generator to the input terminal of another squarewave generator.

Claim 13

A high reliability clock pulse generator comprised of a plurality of clock pulse generators, each generator being a squarewave generator having an RC feedback circuit from an output terminal to an input terminal for continued oscillation at a frequency determined in part by the time constant of said RC feedback circuit, and resistance means connecting the feedback circuit of each squarewave generator to the input terminal of all other squarewave generators, wherein each of said clock pulse generators is comprised of two inverter sections in cascade, each section having an input terminal and an output terminal, and said RC feedback circuit is comprised of a capacitor and a series resistor between the output terminal of the second inverter section to the input terminal of the second inverter section.

Claim 14

A high reliability clock pulse generator comprised of a plurality of clock pulse generators, each generator being a squarewave generator having an RC feedback circuit from an output terminal to an input terminal for continued oscillation at a frequency determined in part by the time constant of said RC feedback circuit, and resistance means connecting the feedback circuit of each squarewave generator to the input terminal of all other squarewave generators, wherein each of said clock pulse generators is comprised of two inverter sections in cascade, each section having an input terminal and an output terminal, and said RC feedback circuit is comprised of a capacitor and a series resistor between the output terminal of the second inverter section to the input terminal of the second inverter section.

Claim 15

The combination of claim 12 including a second resistor connecting a junction between said capacitor and series resistor to the input terminal of the first inverter section.

Claim 16

The combination of claim 13 wherein said clock pulse generator includes a third inverter section between the first and second inverter sections.

Claim 17

In a digital system, the combination of a plurality of flip-flops operated in parallel to provide continued operation of said system in the event of failure of any one of said flip-flops, each one of said flip-flops having one output terminal AC coupled to all others of said flip-flops operated in parallel to place them in a predetermined one of two states when it is changed to said predetermined state, and separate unidirectional AC coupling means coupling the corresponding output terminal of each of said flip-flops operated in parallel to a common output terminal.

Claim 18

In a digital system, the combination of a plurality of flip-flops operated in parallel to provide continued operation of said system in the event of failure of any one of said flip-flops, each one of said flip-flops having one output terminal AC coupled to all others of said flip-flops operated in parallel to place them in a predetermined one of two states when it is changed to said predetermined state, and separate unidirectional AC coupling means coupling the corresponding output terminal of each of said flip-flops operated in parallel to a common output terminal.

Claim 19

The combination of claim 15 wherein said unidirectional AC coupling means is comprised of a capacitor in series with a diode and a plurality of load resistors connected in parallel between said common output terminal and circuit ground.

Claim 20

The combination of claim 15 wherein said one output terminal of each flip-flop AC coupled to all others of said flip-flops is so AC coupled by a plurality of capacitors connected in series.

Claim 21

An arrangement of counters, each having a unique set of output terminals AC coupled to a set of common output terminals and all provided with cross-coupled circuits which effect setting of each counter to a predetermined state by each other counter entering said predetermined state on a periodic basis so that the counters are periodically resynchronized to insure continuance of sequential counting despite failure of one counter wherein each respective counter has a clear input terminal and a bias resistor that holds the clear input terminal at an inactive logic level, and has a separate detecting gate with input terminals AC coupled to the respective counter output terminals by differentiating circuits to produce a transition from one logic level to another logic level at the output of the detecting gate when the counter enters the predetermined state, wherein said arrangement further comprises means for AC coupling the output of the detecting gate of each counter to the clear input terminal of each other counter, thereby to provide synchronization between counters on a periodic basis, and wherein each set of output terminals of said counters is AC coupled to said set of common output terminals by a plurality of AC coupled diode-OR gates, a separate diode-OR gate for coupling each counter output terminal to the corresponding one of the set of common output terminals.

Claim 22

An arrangement of counters, each having a unique set of output terminals AC coupled to a set of common output terminals and all provided with cross-coupled circuits which effect setting of each counter to a predetermined state by each other counter entering said predetermined state on a periodic basis so that the counters are periodically resynchronized to insure continuance of sequential counting despite failure of one counter wherein each respective counter has a clear input terminal and a bias resistor that holds the clear input terminal at an inactive logic level, and has a separate detecting gate with input terminals AC coupled to the respective counter output terminals by differentiating circuits to produce a transition from one logic level to another logic level at the output of the detecting gate when the counter enters the predetermined state, wherein said arrangement further comprises means for AC coupling the output of the detecting gate of each counter to the clear input terminal of each other counter, thereby to provide synchronization between counters on a periodic basis, and wherein each set of output terminals of said counters is AC coupled to said set of common output terminals by a plurality of AC coupled diode-OR gates, a separate diode-OR gate for coupling each counter output terminal to the corresponding one of the set of common output terminals.