Patent US4207435A successfully refreshed from Google Patents.
US4207435A
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US
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Channel translators for use in time division digital exchangers
Assignee: NTT Inc
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Filing: 1978-08-08
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Granted: 1980-06-10
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Expires: 1998-08-08
Abstract
Abstract PCM 24 channel digital voice information received from an incoming trunk are sequentially stored in a speech data memory device for respective channels through an input buffer memory device. The addressed content of the speech data memory device is read out by a control signal which has been stored in a control memory device and adapted to designate an address of the speech data memory device from which information is to be read out, and the read out information is sent to an outgoing trunk through an output buffer memory device thereby operating channel translation. The channel assigned to the outgoing trunk is different from that assigned to the incoming trunk. The speech data memory device, the control memory device and the program memory device are constituted by one memory means and the exchange of signals between the memory means and the input/output buffer memory devices as well as an arithmetic operation unit is effected by a programmed control of a program memory device.
Inventors
- 👤 Keiji Okada
- 👤 Kohei Habara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 09:21
CPC Classifications
H; H04; H04Q; H04Q11/00; H04Q11/04; H04Q11/0407
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
244 words
A channel translator for use in a time division digital exchanger of the type wherein digital information containing digitized voice information assigned to a predetermined channel of a first time division multiplexed digital transmission line is reassigned to any channel of a second digital transmission line thereby effecting telephone exchange, said channel translator comprising: an input buffer memory device for temporarily storing digital information received from the first digital transmission line; a speech data memory device for storing the digital information previously stored in said input buffer memory device; a control memory device for storing channel translation control information which is used to effect channel translation of said digital information stored in said speech data memory device; an output buffer memory device for temporarily storing digital information read out from said speech data memory device and then sending said digital information to said second transmission line; a program memory device for storing a program for controlling the operational sequence of the various circuit elements described above; a processor means adapted to directly access each of said memory devices under the control of said program memory device for reading digital information stored in said input buffer memory device to transfer it to said speech data memory device in synchronism with said predetermined channel of said first digital transmission line and for transferring said digital information from said speech data memory device to said output buffer memory device; and means for electrically connecting said circuit elements.
Claim 2
Dependent Claim
244 words
A channel translator for use in a time division digital exchanger of the type wherein digital information containing digitized voice information assigned to a predetermined channel of a first time division multiplexed digital transmission line is reassigned to any channel of a second digital transmission line thereby effecting telephone exchange, said channel translator comprising: an input buffer memory device for temporarily storing digital information received from the first digital transmission line; a speech data memory device for storing the digital information previously stored in said input buffer memory device; a control memory device for storing channel translation control information which is used to effect channel translation of said digital information stored in said speech data memory device; an output buffer memory device for temporarily storing digital information read out from said speech data memory device and then sending said digital information to said second transmission line; a program memory device for storing a program for controlling the operational sequence of the various circuit elements described above; a processor means adapted to directly access each of said memory devices under the control of said program memory device for reading digital information stored in said input buffer memory device to transfer it to said speech data memory device in synchronism with said predetermined channel of said first digital transmission line and for transferring said digital information from said speech data memory device to said output buffer memory device; and means for electrically connecting said circuit elements.
Claim 3
Dependent Claim
50 words
A channel translator as recited in claim 1 wherein said speech data memory device, said control memory device and said program memory device are embodied in a single memory means, and said input buffer memory device, said output buffer memory device and said memory means are interconnected by bus lines.
Claim 4
Dependent Claim
31 words
A channel translator as recited in claim 1 wherein said processor means includes an arithmetic logic unit for performing the arithmetic operation necessary to cause the desired transfers of digital information.
Claim 5
Dependent Claim
74 words
A channel translator as recited in claim 3 wherein said processor means further includes a multiplexer for converting digital information serially output from said input buffer memory device into parallel output form for input to said speech data memory device and for reading out and converting the digital information stored in parallel in said speech data memory device into a serial form different than that of the information received from said first transmission line.
Claim 6
Dependent Claim
229 words
A channel translator comprising: input buffer means for receiving and temporarily storing an input frame of digital data including a series of quantities of channel data arranged in a predetermined order; output buffer means; first memory means having a plurality of discrete storage sites each adapted for storing one of said quantities of channel data; second memory means for storing a plurality of discrete quantities of channel address information, each corresponding to one of said storage sites; processing means for coupling the output of said input buffer means to said first memory means during first periods of time and for coupling said first memory means to said output means during second periods of time; and third memory means containing a series of instructions for controlling the operation of said input buffer means, said output buffer means, said first memory means, said second memory means and said processing means in accordance with a predetermined sequence such that during said first periods of time the quantities of channel data in said input frame are coupled from said input buffer means into corresponding storage sites of said first memory means and such that during other periods of time, the stored channel data is read out of said storage sites in an order determined by the instructions contained in said third memory means and is coupled to said output buffer means for transmission.
Claim 7
Dependent Claim
229 words
A channel translator comprising: input buffer means for receiving and temporarily storing an input frame of digital data including a series of quantities of channel data arranged in a predetermined order; output buffer means; first memory means having a plurality of discrete storage sites each adapted for storing one of said quantities of channel data; second memory means for storing a plurality of discrete quantities of channel address information, each corresponding to one of said storage sites; processing means for coupling the output of said input buffer means to said first memory means during first periods of time and for coupling said first memory means to said output means during second periods of time; and third memory means containing a series of instructions for controlling the operation of said input buffer means, said output buffer means, said first memory means, said second memory means and said processing means in accordance with a predetermined sequence such that during said first periods of time the quantities of channel data in said input frame are coupled from said input buffer means into corresponding storage sites of said first memory means and such that during other periods of time, the stored channel data is read out of said storage sites in an order determined by the instructions contained in said third memory means and is coupled to said output buffer means for transmission.
Claim 8
Dependent Claim
83 words
A channel translator as recited in claim 5 wherein said processing means causes said frame of digital data to be serially read out of said input buffer means in said predetermined order with each said quantity of channel data being input to a different storage site of said first memory means during time separated periods and causes the quantities of data stored in said first memory means to be read out in a different order during the times separating said time separated periods.
Claim 9
Dependent Claim
61 words
A channel translator as recited in claim 6 wherein said processing means includes multiplexing means for converting the serial frame of data into a plurality of separate channels of data for parallel input to said first memory means and for converting the parallel output of said first memory means into a different serial form for input to said output buffer means.
Claim 10
Dependent Claim
50 words
A channel translator as recited in claim 5 wherein said processing means includes an arithmetic logic unit for determining when a complete frame of channel data has been loaded into said first memory means and when a complete frame of translated data has been loaded into said output buffer means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-06-10 | 1983-12-10 | 1984-06-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-06-10 | 1987-12-10 | 1988-06-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-06-10 | 1991-12-10 | 1992-06-10 | $7700.00 | Window Closed / Lapsed |