Television signal determination in an automatic tuning system

Claim 2

A television signal determination circuit in an automatic tuning system comprising: a first counter means for counting the number of received synchronizing signals; a reference clock signal generator for developing reference clock pulses of a predetermined frequency; a second counter means for counting said reference clock pulses derived from said reference clock signal generator; count operation control means for initiating count operations of said first and second counter means at the same time upon receiving the synchronizing signal; and a determination means for comparing contents of said first and second counter means and developing a signal determination output representing whether received signals are the true television synchronizing signal.

Claim 3

The television signal determination circuit of claim 1, wherein: said first counter means comprises a frequency divicer for developing a first count output upon counting said synchronizing signal by a preselected number; said second counter means comprises a frequency divider for developong a second count output upon counting said reference clock pulses by a predetermined number; and said determination means detects whether said first count output appears before said second count output.

Claim 4

The television signal determination circuit of claim 1 or 2, wherein said synchronizing signal comprises a vertical synchronizing signal.

Claim 5

The television signal determination circuit of claim 1 or 2, wherein said synchronizing signal comprises a horizontal synchronizing signal.

Claim 6

A television signal determination circuit in an automatic tuning system comprising: a first counter means for counting the number of received synchronizing signal and developing a first count output when the count number reaches a preselected number; a clock pulse generator for developing a reference clock pulse signal; a second counter means for counting said reference clock pulse signal derived from said clock pulse generator and developing a second count output when the count number reaches a predetermined number; count control means for initiating count operation of said second counter means in synchronization with count operation of said first counter means; a delayed pulse generator means for developing a delayed pulse of a predetermined pulsewidth in response to development of said second count output from said second counter means; a first control signal generation means for developing a first control signal when said first count output is sensed while said delyaed pulse is developed from said delayed pulse generation means; a second control signal generation means for developing a second control signal when said first count output is not sensed while said delayed pulse is developed from said delayed pulse generation means; and reset means for resetting count operation of said first and second counter means in response to said first and second control signals.

Claim 7

A television signal determination circuit in an automatic tuning system comprising: a first counter means for counting the number of received synchronizing signal and developing a first count output when the count number reaches a preselected number; a clock pulse generator for developing a reference clock pulse signal; a second counter means for counting said reference clock pulse signal derived from said clock pulse generator and developing a second count output when the count number reaches a predetermined number; count control means for initiating count operation of said second counter means in synchronization with count operation of said first counter means; a delayed pulse generator means for developing a delayed pulse of a predetermined pulsewidth in response to development of said second count output from said second counter means; a first control signal generation means for developing a first control signal when said first count output is sensed while said delyaed pulse is developed from said delayed pulse generation means; a second control signal generation means for developing a second control signal when said first count output is not sensed while said delayed pulse is developed from said delayed pulse generation means; and reset means for resetting count operation of said first and second counter means in response to said first and second control signals.

Claim 8

The television signal determination circuit of claim 5, wherein said first and second counter means comprise frequency dividers, respectively.

Claim 9

The television signal determination circuit of claim 5, wherein said delayed pulse generation means comprises a frequency divider and an R-S flip-flop.

Claim 10

The television signal determination circuit of claim 5, 6 or 7, wherein said synchronizing signal comprises a vertical synchronizing signal.

Claim 11

The television signal determination circuit of claim 5, 6 or 7, wherein said synchronizing signal comprises a horizontal synchronizing signal.

Claim 12

The television signal determination circuit of claim 1, 2, 5, 6 or 7, which further comprises a waveform shaping circuit for shaping said received synchronizing signal to be applied to said first counter means.

Claim 13

The television signal determination circuit of claim 10, wherein said waveform shaping circuit comprises a one-shot pulse generator responsive to said synchronizing signal.

Claim 14

A television signal determination circuit in an automatic tuning system including a vertical synchronization signal comprising: counter means for counting the number of received vertical synchronization signals; and determination means for determining whether a preselected number of vertical synchronization signals are counted by said counter means in a predetermined time.

Claim 15

A television signal determination circuit in an automatic tuning system including a vertical synchronization signal comprising: counter means for counting the number of received vertical synchronization signals; and determination means for determining whether a preselected number of vertical synchronization signals are counted by said counter means in a predetermined time.

Claim 16

A television signal determination circuit in an automatic tuning system including a horizontal synchronization signal comprising: counter means for counting the number of received horizontal synchronization signals; and determination means for determining whether a preselected number of horizontal synchronization signals are counted by said counter means in a predetermined time.

Claim 17

A television signal determination circuit in an automatic tuning system including a horizontal synchronization signal comprising: counter means for counting the number of received horizontal synchronization signals; and determination means for determining whether a preselected number of horizontal synchronization signals are counted by said counter means in a predetermined time.