Pulse signal amplifier

Claim 1

A pulse signal amplifier comprising: (a) DC voltage source means having a pair of first and second terminals; (b) pulse signal source means for supplying a pulse signal to be amplified; (c) pre-drive means including a pair of complementary first and second drive transistors each having control, first and second output electrodes, the control electrodes of which are supplied with the pulse signal from said pulse signal source means, the first output electrodes of which are connected to each other and to a reference point, and the second output electrodes of which are connected to the first and second terminals of said DC voltage source means through first and second loads, respectively; (d) drive means including a pair of complementary third and fourth drive transistors each having control, first and second output electrodes, the control electrodes of which are connected to the second output electrodes of said first and second drive transistors and the first output electrodes of which are connected to the first and second terminals of said DC voltage source means, respectively; (e) output stage means including a pair of complementary first and second transistors each having base, emitter and collector electrodes, the base electrodes of which are connected to the second output electrodes of said third and fourth drive transistors, respectively, and collector and emitter circuits of which are connected in series between the first and second terminals of said DC voltage source means, and the connection point of which is connected to an output terminal to which an inductive load is connected; (f) first and second diode means connected between the collector and emitter electrodes of said first and second output transistors, respectively, through the first diode means of which flows a first bypass current from said inductive load during the first quarter-period of the pulse signal from said pulse signal source means and through the second diode means of which flows a second bypass current from said inductive load during the third quarter-period of said pulse signal source means; and (g) current limiting means connected between the second output electrodes of said third and fourth drive transistors such that said first and second bypass currents are prevented from flowing through the base-emitter circuit of said second and first output transistors, respectively, into the second output electrodes of said third and fourth drive transistors.