Digital control device for d.c. thyristor-pulse converter

Claim 1

A digital control device for controlling a d.c. thyristor-pulse converter, comprising: a decoder having first and second information inputs, a first time-shiftable control pulse output, a second time-shiftable control pulse output, a first switching output of control pulses for switching control stages, and a second switching output of control pulses for switching control stages; a clock pulse counter having an input, a first time-fixed control pulse output, a second time-fixed control pulse output, and information outputs connected to said first information inputs of said decoder; a master oscillator having an input, and an output connected to said input of said clock pulse counter; a reversible counter having a reset input connected to said first switching output of said decoder, an initial state setting input, a subtract input, an add input, and information outputs connected to said second information inputs of said decoder; a control unit having a position selection output, a position return output, and an initial position setting output connected to said input of said master oscillator and to said initial position setting input of said reversible counter; a control pulse switching unit comprising first and second flip-flops and first, second, third, fourth, fifth and sixth AND gates; wherein said first flip-flop has a counting input and an output; said second flip-flop has a counting input and an output; said first AND gate of said control pulse switching units has a first input connected to said second time-shiftable control pulse output of said decoder, a second input, and an output connected to a control electrode of a first thyristor of the converter and to said counting input of said first flip-flop, said control electrode also being connected to said first output of said clock pulse counter; said second AND gate of said control pulse switching unit has a first input connected to said first time-shiftable control pulse output of said decoder, a second input, and an output connected to a control electrode of a second thyristor of the converter and to said counting input of said second flip-flop, said control electrode also being connected to said second output of said clock pulse counter; said third AND gate of said control pulse switching unit has a first input connected to said output of said second flip-flop, a second input, and an output connected to a control electrode of a third thyristor of the converter; said fourth AND gate of said control pulse switching unit has a first input connected to said output of said first flip-flop, a second input, and an output connected to a control electrode of a fourth thyristor of the converter; said fifth AND gate of said control pulse switching unit has a first input connected to said first time-shiftable control pulse output of said decoder, a second input, and an output connected to said control electrodes of said first and third thyristors of the converter; and said sixth AND gate of said control pulse switching unit has a first input connected to said second time-shiftable control pulse output of said decoder, a second input, and an output connected to said control electrodes of said second and fourth thyristors of the converter; and a matching unit for matching the states of said control pulse switching unit and of said reversible counter with the state of said control unit comprising a sign flip-flop and first, second, third and fourth AND gates; wherein said sign flip-flop of said matching units has a first input connected to said first switching output of said decoder, a second input connected to said second switching output of said decoder and to said initial state setting output of said control unit, a first output connected to said second inputs of said first, second, third and fourth AND gates of said control pulse switching unit, and a second output connected to said second inputs of said fifth and sixth AND gates of said control pulse switching unit; said first AND gate of said matching unit has a first input connected to said position selection output of said control unit, a second input connected to said second output of said sign flip-flop, and an output connected to said subtract input of said reversible counter; said second AND gate of said matching unit has a first input connected to said position selection output of said control unit, a second input connected to said first output of said sign flip-flop, and an output connected to said add input of said reversible counter; said third AND gate of said matching unit has a first input connected to said position return output of said control unit, a second input connected to said first output of said sign flip-flop, and an output connected to said subtract input of said reversible counter; and said fourth AND gate of said matching unit has a first input connected to said position return output of said control unit, a second input connected to said second ouput of said sign flip-flop, and an output connected to said add input of said reversible counter.