Phase-locked loop clock pulse extraction circuit

Claim 2

A circuit for extracting a clock pulse waveform from an input pulse waveform comprising: a phase-locked loop including a phase comparator having a first input to which said input waveform is coupled, a second input and an output which is coupled in cascade with at least a voltage controlled oscillator whose output is coupled to said second input, said clock waveform being present at said output of said oscillator and having negative going transitions occurring substantially in the middle of the pulses of said input waveform; said phase comparator including gating means coupled to said first and second inputs controlled by said clock waveform and said input waveform to produce first and second intermediate pulse waveforms each having pulses constituted by different portions of the pulses of said input waveform and proportional to the pulse density of said input waveform, filter means connected directly to said gate means responsive to said first and second intermediate waveforms to produce first and second output waveforms which are equal to the mean amplitude values of said first and second intermediate waveforms, and subtractor means coupled to said filter means to produce a comparator output signal at said output of said comparator which is a function of the ratio of said first and second output waveforms and independent of the pulse density of said input waveform, said gating means including first and second gates each receiving said input waveform, said first and second gates being interconnected such that one of said first and second gates receives said clock waveform to control both of said first and second gates to produce said first intermediate waveform at the output of one of said first and second gates and said second intermediate waveform at the output of the other of said first and second gates, and said filter means includes first and second filter circuits each coupled to a different one of the outputs of said first and second gates to produce said first output waveform at the output of one of said first and second filter circuits and said second output waveform at the output of the other of said first and second filter circuits.

Claim 3

A circuit according to claim 1, wherein one of said first and second filter circuits produces therein a first filter signal proportional to the logarithm of one of said first and second output waveforms, and the other of said first and second filter circuits produces therein a second filter signal proportional to the logarithm of the other of said first and second output waveforms.

Claim 4

A circuit for extracting a clock pulse waveform from an input pulse waveform comprising: a phase-locked loop including a phase comparator having a first input to which said input waveform is coupled, a second input and an output which is coupled in cascade with at least a voltage controlled oscillator whose output is coupled to said second input, said clock waveform being present at said output of said oscillator and having negative going transitions occurring substantially in the middle of the pulses of said input waveform; said phase comparator including gating means coupled to said first and second inputs controlled by said clock waveform and said input waveform to produce first and second intermediate pulse waveforms each having pulses constituted by different portions of the pulses of said input waveform and proportional to the pulse density of said input waveform, filter means connected directly to said gate means responsive to said first and second intermediate waveforms to produce first and second output waveforms which are equal to the mean amplitude values of said first and second intermediate waveforms, and subtractor means coupled to said filter means to produce a comparator output signal at said output of said comparator which is a function of the ratio of said first and second output waveforms and independent of the pulse density of said input waveform; said gating means including first and second gating circuits each receiving said input waveform, said first and second gating circuits being interconnected such that one of said first and second gating circuits receives said clock waveform to control both of said first and second gating circuits to produce said first intermediate waveform at the output of one of said first and second gating circuits and said second intermediate waveform at the output of the other of said first and second gating circuits, and said filter means including first and second filter circuits each coupled to a different one of the outputs of said first and second gating circuits to produce said first output waveform at the output of one of said first and second filter circuits and said second output waveform at the output of the other of said first and second filter circuits one of said first and second filter circuits producing therein a first filter signal proportional to the logarithm of one of said first and second output waveforms, and the other of said first and second filter circuits producing therein a second filter signal proportional to the logarithm of the other of said first and second output waveform; each of said and second filter circuits including a first branch having at least a capacitor, and a second branch having at least a first resistor and a diode connected in series, one of said first and second output waveforms flowing in one of said second branches and the other of said first and second output waveforms flowing in the other of said second branches, and one of said first and second filter signals being generated across one of said diodes and the other of said first and second filter signals being generated across the other of said diodes.

Claim 5

A circuit for extracting a clock pulse waveform from an input pulse waveform comprising: a phase-locked loop including a phase comparator having a first input to which said input waveform is coupled, a second input and an output which is coupled in cascade with at least a voltage controlled oscillator whose output is coupled to said second input, said clock waveform being present at said output of said oscillator and having negative going transitions occurring substantially in the middle of the pulses of said input waveform; said phase comparator including gating means coupled to said first and second inputs controlled by said clock waveform and said input waveform to produce first and second intermediate pulse waveforms each having pulses constituted by different portions of the pulses of said input waveform and proportional to the pulse density of said input waveform, filter means connected directly to said gate means responsive to said first and second intermediate waveforms to produce first and second output waveforms which are equal to the mean amplitude values of said first and second intermediate waveforms, and subtractor means coupled to said filter means to produce a comparator output signal at said output of said comparator which is a function of the ratio of said first and second output waveforms and independent of the pulse density of said input waveform; said gating means including first and second gating circuits each receiving said input waveform, said first and second gating circuits being interconnected such that one of said first and second gating circuits receives said clock waveform to control both of said first and second gating circuits to produce said first intermediate waveform at the output of one of said first and second gating circuits and said second intermediate waveform at the output of the other of said first and second gating circuits, and said filter means including first and second filter circuits each coupled to a different one of the outputs of said first and second gating circuits to produce said first output waveform at the output of one of said first and second filter circuits and said second output waveform at the output of the other of said first and second filter circuits one of said first and second filter circuits producing therein a first filter signal proportional to the logarithm of one of said first and second output waveforms, and the other of said first and second filter circuits producing therein a second filter signal proportional to the logarithm of the other of said first and second output waveform; each of said and second filter circuits including a first branch having at least a capacitor, and a second branch having at least a first resistor and a diode connected in series, one of said first and second output waveforms flowing in one of said second branches and the other of said first and second output waveforms flowing in the other of said second branches, and one of said first and second filter signals being generated across one of said diodes and the other of said first and second filter signals being generated across the other of said diodes.

Claim 6

A circuit according to claim 3, wherein each of said diodes is constituted by the base-to-emitter junction of a different one of two transistors.

Claim 7

A circuit according to claim 3, wherein said subtractor means includes a differential amplifier having one of its inputs coupled to one of said second branches and the other of the inputs coupled to the other of said second branches to provide said comparator output signal at its output.

Claim 8

A circuit according to claim 3, wherein in each of said second branches the resistance value of said first resistor is much greater than the resistance value of said diode.

Claim 9

A circuit according to claim 3, wherein each of said branches further includes a second resistor connected in series with said capacitor, and said output of said phase comparator is directly connected to said oscillator.

Claim 10

A circuit according to claim 3, wherein said phase-locked loop further includes a filter network coupled between said output of said phase comparator and said oscillator to provide a second order phase-locked loop.

Claim 11

A circuit for extracting a clock pulse waveform from an input waveform having zero pulses, positive mark pulses and negative mark pulses present, at an input to said circuit comprising: means coupled to said circuit input to shape and rectify said input waveform to produce a current pulse waveform corresponding to said input waveform; and a phase-locked loop including a phase comparator having a first input coupled to said means to receive said current waveform, a second input and an output which is coupled in cascade with at least a voltage controlled oscillator whose output is coupled to said second input, said clock waveform being present at said output of said oscillator and having negative going transitions occurring substantially in the middle of the pulses of said current waveform; said phase comparator including gating means coupled to said first and second inputs controlled by said clock waveform and said current waveform to produce first and second intermediate pulse waveforms each having pulses constituted by different portions of the pulses of said current waveform and proportional to the pulse density of said input waveform, filter means coupled to said gate means responsive to said first and second intermediate waveforms to produce first and second output waveforms which are equal to the means amplitude values of said first and second intermediate waveforms, and substractor means coupled to said filter means to produce a comparator output signal at said output of said comparator which is a function of the ratio of said first and second output waveforms and independent of the pulse density of said input waveform.

Claim 12

A circuit for extracting a clock pulse waveform from an input waveform having zero pulses, positive mark pulses and negative mark pulses present, at an input to said circuit comprising: means coupled to said circuit input to shape and rectify said input waveform to produce a current pulse waveform corresponding to said input waveform; and a phase-locked loop including a phase comparator having a first input coupled to said means to receive said current waveform, a second input and an output which is coupled in cascade with at least a voltage controlled oscillator whose output is coupled to said second input, said clock waveform being present at said output of said oscillator and having negative going transitions occurring substantially in the middle of the pulses of said current waveform; said phase comparator including gating means coupled to said first and second inputs controlled by said clock waveform and said current waveform to produce first and second intermediate pulse waveforms each having pulses constituted by different portions of the pulses of said current waveform and proportional to the pulse density of said input waveform, filter means coupled to said gate means responsive to said first and second intermediate waveforms to produce first and second output waveforms which are equal to the means amplitude values of said first and second intermediate waveforms, and substractor means coupled to said filter means to produce a comparator output signal at said output of said comparator which is a function of the ratio of said first and second output waveforms and independent of the pulse density of said input waveform.