Patent US4201884A successfully refreshed from Google Patents.
US4201884A
Expired / Lapsed
US
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Digital data transmission system
Assignee: STC PLC
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Filing: 1977-11-07
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Granted: 1980-05-06
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Expires: 1997-11-07
Abstract
Abstract The position of a pulse, relative to a reference time, defines a digital data state. The position alternates about the reference time such that by monitoring the mean pulse position the reference time may be regenerated in the receiver. The reference time is then used to decode the transmitted signal.
Inventors
- 👤 Philip R. Couch
- 👤 David A. Philpott
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 23:50
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/38; H04L25/40; H04L25/49; H04L25/4902
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
149 words
A digital data transmission system comprising: a transmitter including first means for producing a polyphase clock, and logic gating means coupled to said first means for gating digital data input signals with said polyphase clock to provide a transmission signal, one data state of said input signals being gated with one clock phase of said polyphase clock, said one clock being time coincident with a reference time, and the other data state of said input signals being alternately gated with other clock phases of said polyphase clock, said other clock phases being equally distributed in time about said reference time; and a receiver including second means coupled to said logic gating means for extracting from signals received from said transmitter a reference clock signal corresponding to said one clock phase, and third means coupled to said second means for sampling said received signal with said extracted reference clock signal.
Claim 2
Dependent Claim
149 words
A digital data transmission system comprising: a transmitter including first means for producing a polyphase clock, and logic gating means coupled to said first means for gating digital data input signals with said polyphase clock to provide a transmission signal, one data state of said input signals being gated with one clock phase of said polyphase clock, said one clock being time coincident with a reference time, and the other data state of said input signals being alternately gated with other clock phases of said polyphase clock, said other clock phases being equally distributed in time about said reference time; and a receiver including second means coupled to said logic gating means for extracting from signals received from said transmitter a reference clock signal corresponding to said one clock phase, and third means coupled to said second means for sampling said received signal with said extracted reference clock signal.
Claim 3
Dependent Claim
27 words
A system according to claim 1, wherein the number of phases in said polyphase clock is three, and said digital data input signals are binary coded signals.
Claim 4
Dependent Claim
97 words
A digital data transmitter comprising: means for producing a polyphase clock, and logic gating means coupled to said means for producing for gating digital data input signals with said polyphase clock to provide a transmission signal, one data state of said input signals being gated with one clock phase of said polyphase clock, said one clock phase being time coincident with a reference time, and the other data state of said input signals being alternately gated with other clock phases of said polyphase clock, said other clock phases being equally distributed in time about said reference time.
Claim 5
Dependent Claim
97 words
A digital data transmitter comprising: means for producing a polyphase clock, and logic gating means coupled to said means for producing for gating digital data input signals with said polyphase clock to provide a transmission signal, one data state of said input signals being gated with one clock phase of said polyphase clock, said one clock phase being time coincident with a reference time, and the other data state of said input signals being alternately gated with other clock phases of said polyphase clock, said other clock phases being equally distributed in time about said reference time.
Claim 6
Dependent Claim
27 words
A transmitter according to claim 3, wherein the number of phases in said polyphase clock is three, and said digital data input signals are binary coded signals.
Claim 7
Dependent Claim
109 words
A digital data receiver receiving a signal having one data state of a digital data signal being represented by one clock phase of a polyphase clock, said one clock phase being time coincident with a reference time, and the other data state of said digital data signal being alternately represented by other clock phases of said polyphase clock, said other clock phases being equally distributed in time about said reference time, comprising: first means for extracting from said received signal a reference clock signal corresponding to said one clock phase; and second means coupled to said first means for sampling said received signal with said extracted reference clock signal.
Claim 8
Dependent Claim
109 words
A digital data receiver receiving a signal having one data state of a digital data signal being represented by one clock phase of a polyphase clock, said one clock phase being time coincident with a reference time, and the other data state of said digital data signal being alternately represented by other clock phases of said polyphase clock, said other clock phases being equally distributed in time about said reference time, comprising: first means for extracting from said received signal a reference clock signal corresponding to said one clock phase; and second means coupled to said first means for sampling said received signal with said extracted reference clock signal.
Claim 9
Dependent Claim
27 words
A receiver according to claim 5, wherein the number of phases of said polyphase clock is three, and said digital data signal is a binary coded signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-05-06 | 1983-11-05 | 1984-05-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-05-06 | 1987-11-05 | 1988-05-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-05-06 | 1991-11-05 | 1992-05-06 | $7700.00 | Window Closed / Lapsed |