Digital predecoding system

Claim 2

A circuit for providing address signals to a memory array, comprising: a plurality of OR gates for predecoding a first portion of an address signal received in a coded format; a plurality of NOR gates each coupled to a respective one of the plurality of OR gates, the plurality of NOR gates providing at least one output; and a plurality of means each coupled to one of the plurality of NOR gates, each of the plurality of means for ANDing the at least one output with a signal to route a decoded address signal to a predetermined line of storage cells within the memory array.

Claim 3

The circuit of claim 1 wherein the OR and NOR gates each comprise a plurality of field effect transistors.

Claim 4

A digital memory array address predecoder in combination with a decoder, comprising: at least one logic gate for predecoding first address signals and having at least a first and a second field effect transistor to receive the first address signals, and having a third transistor for precharging an output node of the at least one logic gate; at least a second logic gate having an input coupled to the output node of the at least one logic gate, the at least a second logic gate having at least a fourth field effect transistor for receiving other predecoded address signals, the at least a second logic gate having an output; and a last field effect transistor having a first electrode, a second electrode, and a gate electrode wherein the gate electrode is coupled to the output of the at least a second logic gate, the first electrode of the last field effect transistor being coupled to an address array line select signal, and the second electrode of the last field effect transistor being coupled to the memory array.

Claim 5

A digital memory array address predecoder in combination with a decoder, comprising: at least one logic gate for predecoding first address signals and having at least a first and a second field effect transistor to receive the first address signals, and having a third transistor for precharging an output node of the at least one logic gate; at least a second logic gate having an input coupled to the output node of the at least one logic gate, the at least a second logic gate having at least a fourth field effect transistor for receiving other predecoded address signals, the at least a second logic gate having an output; and a last field effect transistor having a first electrode, a second electrode, and a gate electrode wherein the gate electrode is coupled to the output of the at least a second logic gate, the first electrode of the last field effect transistor being coupled to an address array line select signal, and the second electrode of the last field effect transistor being coupled to the memory array.

Claim 6

A digital memory array address predecoder in combination with a decoder, comprising: at least one logic gate for predecoding first address signals and having at least a first and a second field effect transistor to receive the first address signals, and having a third transistor for precharging an output node of the at least one logic gate; at least a second logic gate having an input coupled to the output node of the at least one logic gate, the at least a second logic gate having at least a fourth field effect transistor for receiving other predecoded address signals, the at least a second logic gate having an output; and a last field effect transistor having a first electrode, a second electrode, and a gate electrode wherein the gate electrode is coupled to the output of the at least a second logic gate, the first electrode of the last field effect transistor being coupled to an address array line select signal, and the second electrode of the last field effect transistor being coupled to the memory array, the at least one logic gate is an OR gate, the at least a second logic gate is a NOR gate, and the last field effect transistor performs a logic AND function.

Claim 7

A digital memory array address predecoder in combination with a decoder, comprising: at least one logic gate for predecoding first address signals and having at least a first and a second field effect transistor to receive the first address signals, and having a third transistor for precharging an output node of the at least one logic gate; at least a second logic gate having an input coupled to the output node of the at least one logic gate, the at least a second logic gate having at least a fourth field effect transistor for receiving other predecoded address signals, the at least a second logic gate having an output; and a last field effect transistor having a first electrode, a second electrode, and a gate electrode wherein the gate electrode is coupled to the output of the at least a second logic gate, the first electrode of the last field effect transistor being coupled to an address array line select signal, and the second electrode of the last field effect transistor being coupled to the memory array, the at least one logic gate is an OR gate, the at least a second logic gate is a NOR gate, and the last field effect transistor performs a logic AND function.

Claim 8

A digital decoding system for decoding multi-bit parallel channel digital input signals, comprising: a plurality of logic OR gates for receiving and predecoding the digital input signals and each providing an output; and a plurality of logic NOR gates each coupled to a respective one of the plurality logic OR gates for receiving the output of each respective one of the plurality of logic OR gates; and a plurality of gated output circuits each coupled to a respective one of the plurality of logic NOR gates for passing decoded outputs upon predetermined commands.

Claim 9

A digital decoding system for decoding multi-bit parallel channel digital input signals, comprising: a plurality of logic OR gates for receiving and predecoding the digital input signals and each providing an output; and a plurality of logic NOR gates each coupled to a respective one of the plurality logic OR gates for receiving the output of each respective one of the plurality of logic OR gates; and a plurality of gated output circuits each coupled to a respective one of the plurality of logic NOR gates for passing decoded outputs upon predetermined commands.

Claim 10

A digital decoding system for decoding multi-bit parallel channel digital input signals and having a predecoder, comprising: a first plurality of logic gates each having a first, a second, and a third transistor, each transistor having a first, a second, and a gate electrode, the first electrodes of the first and second transistors being coupled to a first power supply terminal and the second electrodes of the first and second transistors being connected together to form an output node, the first electrode of the third transistor being coupled to the output node, the gate electrode of the third transistor being for receiving a precharge signal, and the gate electrodes of the first and second transistors being for receiving coded digital input signals; and a second plurality of logic gates each having a fourth transistor with a first, a second, and a gate electrode, the gate electrode of the fourth transistor being for receiving the precharge signal and the first electrode being coupled to the first power supply terminal, a fifth transistor having a first, a second, and a gate electrode which is coupled to the output node of a logic gate from the first plurality of logic gates, the first electrode of the fifth transistor being connected to the second electrode of the fourth transistor, and at least a sixth transistor connected in parallel with the fifth transistor and having a gate electrode coupled to another logic gate of the first plurality of logic gates; and at least one output transistor having a gate electrode coupled to the second electrode of the fourth transistor.

Claim 11

A digital decoding system for decoding multi-bit parallel channel digital input signals and having a predecoder, comprising: a first plurality of logic gates each having a first, a second, and a third transistor, each transistor having a first, a second, and a gate electrode, the first electrodes of the first and second transistors being coupled to a first power supply terminal and the second electrodes of the first and second transistors being connected together to form an output node, the first electrode of the third transistor being coupled to the output node, the gate electrode of the third transistor being for receiving a precharge signal, and the gate electrodes of the first and second transistors being for receiving coded digital input signals; and a second plurality of logic gates each having a fourth transistor with a first, a second, and a gate electrode, the gate electrode of the fourth transistor being for receiving the precharge signal and the first electrode being coupled to the first power supply terminal, a fifth transistor having a first, a second, and a gate electrode which is coupled to the output node of a logic gate from the first plurality of logic gates, the first electrode of the fifth transistor being connected to the second electrode of the fourth transistor, and at least a sixth transistor connected in parallel with the fifth transistor and having a gate electrode coupled to another logic gate of the first plurality of logic gates; and at least one output transistor having a gate electrode coupled to the second electrode of the fourth transistor.