Signal generator

Claim 2

Control signal generating means capable of generating a plurality of different timing cycles comprising: multi-stage shift register means having outputs from a plurality of said stages; at least one selectively effective delay means interposed between successive stages of said shift register means; start means coupled to said shift register means for initiating and disabling operation of said shift register means; means for clocking said multi-stage shift register means; multiplexer means to which a plurality of said outputs from various stages of said shift register means are applied and from which said timing cycles are taken; and selection means for controlling said multiplexer means to select desired outputs from the shift register means for application to a utilizing device.

Claim 3

The generating means of claim 1 in which the complement output of the final stage of the shift register means is applied to the input of the first stage.

Claim 4

The generating means of claim 1 including switching means for selectively switching said selectively effective delay means into and out of operative coupling relation to the shift register means.

Claim 5

The generating means of claim 1 in which said selectively effective delay means comprises at least one flip-flop.

Claim 6

The generating means of claim 1 in which the selectively effective delay means comprises at least one flip-flop plus gating means for selectively switching the delay means into and out of operative coupling relation to the shift register means.

Claim 7

The generating means of claim 1 in which the selectively effective delay means comprises a plurality of flip-flops connected in series relationship.

Claim 8

The generating means of claim 1 in which said multiplexer means includes a plurality of multiplexers.

Claim 9

The generating means of claim 1, also including gating means interposed between the shift register means and the multiplexer means to control the transmission of signals from said shift register means to said multiplexer means.

Claim 10

The generating means of claim 1, also including start means coupled to said shift register means for initiating operation of the control signal generating means.

Claim 11

Control signal generating means capable of generating a plurality of different timing cycles comprising: multi-stage shift register means; at least one selectively effective delay means interposed between successive stages of said shift register means; start means coupled to said shift register means for initiating and disabling operation of said shift register means; means for clocking said multi-stage shift regiser means; multiplexer means to which a plurality of outputs from various stages of said shift register means are applied and from which said timing cycles are taken; selection means for controlling said multiplexer means to select desired outputs from the shift register means for application to a utilizing device; and an enable means operatively coupled to said multiplexer means for interrupting the output signals from said shift register means after the desired output has been terminated and before the multi-stage shift register means is disabled.

Claim 12

Control signal generating means capable of generating a plurality of different timing cycles comprising: multi-stage shift register means; at least one selectively effective delay means interposed between successive stages of said shift register means; start means coupled to said shift register means for initiating and disabling operation of said shift register means; means for clocking said multi-stage shift regiser means; multiplexer means to which a plurality of outputs from various stages of said shift register means are applied and from which said timing cycles are taken; selection means for controlling said multiplexer means to select desired outputs from the shift register means for application to a utilizing device; and an enable means operatively coupled to said multiplexer means for interrupting the output signals from said shift register means after the desired output has been terminated and before the multi-stage shift register means is disabled.

Claim 13

The generating means of claim 10 in which the enable means is controlled by said shift register means and said multiplexer means.

Claim 14

Control signal generating means comprising: multi-stage shift register means having an output coupled to at least certain stages thereof, from which control signals may be taken, the complement of the output of the final stage of the shift register means being applied to the input of the first stage; start means coupled to said shift register means for initiating operation of the control signal generating means; oscillator means for clocking said shift register means; at least one delay means interposed between successive stages of said shift register means, said delay means including flip-flop means and gating means, said gating means being connected to one of the stages of said shift register means to which said delay means is coupled, whereby due to the complementary connection between the final stage and the first stage of said shift register means opposite binary values are applied to said gating means from said stage during successive operations of said shift register means, one of said binary values causing said delay means to be operative in imposing a delay between said successive stages, and the other binary value being operable to exclude the effect of said delay means; and means to control whether or not said delay means is operable to impose an additional delay between successive stages of said shift register means.

Claim 15

Control signal generating means comprising: multi-stage shift register means having an output coupled to at least certain stages thereof, from which control signals may be taken, the complement of the output of the final stage of the shift register means being applied to the input of the first stage; start means coupled to said shift register means for initiating operation of the control signal generating means; oscillator means for clocking said shift register means; at least one delay means interposed between successive stages of said shift register means, said delay means including flip-flop means and gating means, said gating means being connected to one of the stages of said shift register means to which said delay means is coupled, whereby due to the complementary connection between the final stage and the first stage of said shift register means opposite binary values are applied to said gating means from said stage during successive operations of said shift register means, one of said binary values causing said delay means to be operative in imposing a delay between said successive stages, and the other binary value being operable to exclude the effect of said delay means; and means to control whether or not said delay means is operable to impose an additional delay between successive stages of said shift register means.

Claim 16

The signal generating means of claim 12 including multiplexer means to which the outputs from the shift register stages are coupled.

Claim 17

The signal generating means of claim 13 including enable means operatively coupled to said multiplexer means for interrupting output signals from the shift register means.

Claim 18

Control signal generating means capable of generating a plurality of different timing cycles comprising: multi-stage shift register means having the complement output of the final stage thereof applied to the input of the first stage; start means coupled to said multi-stage shift register means for initiating and disabling operation of the multi-stage shift register means; oscillator means for clocking said multi-stage shift register means; at least one delay means interposed between successive stages of said shift register means, said delay means including at least one flip-flop plus gating means for selectively switching the delay means into and out of operative coupling relation to the shift register means; multiplexer means to which a plurality of outputs from various stages of said shift register means are applied and from which said timing cycles are taken; enable means operatively coupled to said multiplexer means for interrupting the output signals from said shift register means after the desired output has been terminated and before the multi-stage shift register means is disabled, said enable means being controlled by said shift register means and said multiplexer means; gating means interposed between the shift register means and the multiplexer means to control the transmission of signals from said shift register means to said multiplexer means; and selection means for controlling said multiplexer means to select desired outputs from the shift register means for application to a utilizing device.

Claim 19

Control signal generating means capable of generating a plurality of different timing cycles comprising: multi-stage shift register means having the complement output of the final stage thereof applied to the input of the first stage; start means coupled to said multi-stage shift register means for initiating and disabling operation of the multi-stage shift register means; oscillator means for clocking said multi-stage shift register means; at least one delay means interposed between successive stages of said shift register means, said delay means including at least one flip-flop plus gating means for selectively switching the delay means into and out of operative coupling relation to the shift register means; multiplexer means to which a plurality of outputs from various stages of said shift register means are applied and from which said timing cycles are taken; enable means operatively coupled to said multiplexer means for interrupting the output signals from said shift register means after the desired output has been terminated and before the multi-stage shift register means is disabled, said enable means being controlled by said shift register means and said multiplexer means; gating means interposed between the shift register means and the multiplexer means to control the transmission of signals from said shift register means to said multiplexer means; and selection means for controlling said multiplexer means to select desired outputs from the shift register means for application to a utilizing device.

Claim 20

The control signal generating means of claim 15 including means coupling an output of said multiplexer means to said start means for resetting said start means to disable said multi-stage shift register means.

Claim 21

Control signal generating means capable of generating a plurality of different timing cycles comprising: multi-stage shift register means having outputs from a plurality of said stages and having the complement output of the final stage thereof applied to the input of the first stage; start means coupled to said multi-stage shift register means for initiating operation of the shift register means; oscillator means for clocking said multi-stage shift register means; at least one delay means interposed between successive stages of said shift register means, said delay means including at least one flip-flop plus gating means for selectively switching the delay means into and out of operative coupling relation to the shift register means; multiplexer means to which a plurality of said outputs from various stages of said shift register means are applied and from which said timing cycles are taken; gating means interposed between the shift register means and the multiplexer means to control the transmission of signals from said shift register means to said multiplexer means; and selection means for controlling said multiplexer means to select desired outputs from the shift register means for application to a utilizing device.

Claim 22

Control signal generating means capable of generating a plurality of different timing cycles comprising: multi-stage shift register means having outputs from a plurality of said stages and having the complement output of the final stage thereof applied to the input of the first stage; start means coupled to said multi-stage shift register means for initiating operation of the shift register means; oscillator means for clocking said multi-stage shift register means; at least one delay means interposed between successive stages of said shift register means, said delay means including at least one flip-flop plus gating means for selectively switching the delay means into and out of operative coupling relation to the shift register means; multiplexer means to which a plurality of said outputs from various stages of said shift register means are applied and from which said timing cycles are taken; gating means interposed between the shift register means and the multiplexer means to control the transmission of signals from said shift register means to said multiplexer means; and selection means for controlling said multiplexer means to select desired outputs from the shift register means for application to a utilizing device.