Patent US4190850A successfully refreshed from Google Patents.
US4190850A
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MIS field effect transistor having a short channel length
Assignee: Siemens AG
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Filing: 1978-01-17
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Granted: 1980-02-26
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Expires: 1998-01-17
Abstract
Abstract A MIS field effect transistor having a source zone of a first impurity type formed in a semiconductor substrate immediately below one planar surface thereof, a drain zone of the first conductivity type in said substrate spaced from the source zone immediately below said one surface, a third zone, of said first impurity type in said substrate extending between said source and drain zones and extending deeper in said substrate than either said source or drain zones, a thin buried zone of the second conductivity type in said substrate spaced below and around the ends of said source zone, the region of said buried zone where it lies between said source and drain zones providing a channel whose length is only the thickness of the buried zone in the region where the buried zone reaches the substrate surface. A process for producing such a transistor is also disclosed.
Inventors
- 👤 Jenoe Tihanyi
- 👤 Guido Bell
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 16:47
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/64; H10D30/65; H10D30/01; H10D30/021; H10D30/028; H10D30/657; H10D30/66; H10D30/67; H10D30/6704; H10D30/6713; H10D30/6715; H10D30/6717; H10D30/6758; H10D30/6759; H10D62/00; H10D62/10; H10D62/17; H10D62/393; H10D64/00; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/514; H10D64/516; H10P; H10P30/00; H10P30/20; H10P30/202; H10P30/204; H10P30/21; H10P30/212; H10P30/22; H10P50/00; H10P50/20; H10P50/28; H10P50/282; H10P50/283; H10D62/13; H10D62/149; H10D62/151; H10D64/23; H10D64/251; H10D64/256
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
184 words
MIS field effect transistor having a short channel length with a semiconductor substrate, on the surface of which there is arranged an insulating layer, which is in turn provided with a gate electrode layer, wherein, in the semiconductor substrate there is provided a drain zone of the first conductivity type and a source zone which possesses the first conductivity type is strongly doped and meets the substrate surface, a second doped zone of the second conductivity type which lies below said source zone and surrounds said source zone at least in the direction of said drain zone, and meets the substrate surface spaced laterally with respect to said source zone by a third zone, a channel zone being formed by that portion of the semiconductor substrate which lies between the outer edge of said second doped zone adjoining the substrate surface and the adjacent edge of said source zone, and is located within said third zone of the first conductivity type, said third doped zone being lightly doped and adjoining said drain zone, source zone and said second doped zone containing implanted dopant particles.
Claim 2
Dependent Claim
184 words
MIS field effect transistor having a short channel length with a semiconductor substrate, on the surface of which there is arranged an insulating layer, which is in turn provided with a gate electrode layer, wherein, in the semiconductor substrate there is provided a drain zone of the first conductivity type and a source zone which possesses the first conductivity type is strongly doped and meets the substrate surface, a second doped zone of the second conductivity type which lies below said source zone and surrounds said source zone at least in the direction of said drain zone, and meets the substrate surface spaced laterally with respect to said source zone by a third zone, a channel zone being formed by that portion of the semiconductor substrate which lies between the outer edge of said second doped zone adjoining the substrate surface and the adjacent edge of said source zone, and is located within said third zone of the first conductivity type, said third doped zone being lightly doped and adjoining said drain zone, source zone and said second doped zone containing implanted dopant particles.
Claim 3
Dependent Claim
24 words
MIS field effect transistor as claimed in claim 1, in which the length of said channel zone amounts to between 0.1 and 0.5 μm.
Claim 4
Dependent Claim
35 words
MIS field effect transistor as claimed in claim 1, in which the thickness of said insulating layer above said channel zone gradually reduces in thickness towards said source zone to thereby form a wedge angle.
Claim 5
Dependent Claim
22 words
MIS field effect transistor as claimed in claim 3, in which said wedge angle amounts to between approximately 15° and approximately 60°.
Claim 6
Dependent Claim
18 words
MIS field effect transistor as claimed in claim 3, in which said wedge angle amounts to approximately 20°.
Claim 7
Dependent Claim
29 words
MIS field effect transistor as claimed in claim 1, in which the thickness of said gate electrode above said channel zone is reduced in a wedge-angle towards its edges.
Claim 8
Dependent Claim
35 words
MIS field effect transistor as claimed in claim 6, in which the thickness of said gate electrode layer between said source zone and said drain zone increases continuously in the direction of said drain zone.
Claim 9
Dependent Claim
22 words
MIS field effect transistor as claimed in claim 6, in which said wedge angle amounts to between approximately 15° and approximately 60°.
Claim 10
Dependent Claim
18 words
MIS field effect transistor as claimed in claim 6, in which said wedge angle amounts to approximately 20°.
Claim 11
Dependent Claim
29 words
MIS field effect transistor as claimed in claim 1, in which said drain zone is a buried layer which lies beneath said third doped zone in said semiconductor substrate.
Claim 12
Dependent Claim
30 words
MIS field effect transistor as claimed in claim 1, in which said drain zone is located laterally of said third doped zone and meets said surface of said semiconductor substrate.
Claim 13
Dependent Claim
17 words
MIS field effect transistor as claimed in claim 1, in which said semiconductor substrate consists of silicon.
Claim 14
Dependent Claim
31 words
MIS field effect transistor as claimed in claim 1, said zones of the first conductivity type being doped with n-dopant, and those of the second conductivity type being doped with p-dopant.
Claim 15
Dependent Claim
20 words
MIS field effect transistor as claimed in claim 11, in which said n-dopant is phosphorus and said p-dopant is boron.
Claim 16
Dependent Claim
18 words
MIS field effect transistor as claimed in claim 1, in which said insulating layer consists of silicon dioxide.
Claim 17
Dependent Claim
33 words
MIS field effect transistor as claimed in claim 1, in which said insulating layer is a double layer which consists of a SiO 2 layer and a phosphorus glass layer arranged upon it.
Claim 18
Dependent Claim
19 words
MIS field effect transistor as claimed in claim 1, in which said gate electrode layer consists of polycrystalline silicon.
Claim 19
Dependent Claim
151 words
A field effect transistor having a short channel length comprising a semiconductor substrate, a heavily doped source zone of a first impurity type formed in said semiconductor substrate immediately below one planar surface thereof, a heavily doped drain zone of the first conductivity type in said substrate spaced from the source zone immediately below said one surface, a lightly doped third zone of said first impurity type in said substrate extending between said source and drain zones and extending deeper in said substrate than either said source or drain zones, a thin buried zone of the second conductivity type in said substrate spaced below and around the ends of said source zone, the region of said buried zone where it lies between said source and drain zones providing a channel whose length is only the thickness of the buried zone in the region where the buried zone reaches the substrate surface.
Claim 20
Dependent Claim
151 words
A field effect transistor having a short channel length comprising a semiconductor substrate, a heavily doped source zone of a first impurity type formed in said semiconductor substrate immediately below one planar surface thereof, a heavily doped drain zone of the first conductivity type in said substrate spaced from the source zone immediately below said one surface, a lightly doped third zone of said first impurity type in said substrate extending between said source and drain zones and extending deeper in said substrate than either said source or drain zones, a thin buried zone of the second conductivity type in said substrate spaced below and around the ends of said source zone, the region of said buried zone where it lies between said source and drain zones providing a channel whose length is only the thickness of the buried zone in the region where the buried zone reaches the substrate surface.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-02-25 | 1983-08-27 | 1984-02-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-02-25 | 1987-08-27 | 1988-02-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-02-25 | 1991-08-27 | 1992-02-26 | $7700.00 | Window Closed / Lapsed |