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US4190778A Expired / Lapsed US ⏱️ 0.0 years remaining

A.C. supplied integrated semi-conductor logic circuit

Assignee: Siemens AG
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Filing: 1978-06-12
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Granted: 1980-02-26
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Expires: 1998-06-12
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Abstract

Abstract An integrated semiconductor circuit arrangement includes active and passive function elements in a semiconductor body and a high frequency a.c. voltage is used as a supply voltage for the function elements. A highly doped semiconductor substrate of one conductivity type carries a weakly doped layer, for example, of the same conductivity which has zones of the opposite conductivity therein. The substrate functions as an emitter for a plurality of transistors of which the doped zones serve as bases. Spaced co-planar layer sections bridge the base zones and serve as collectors. The collectors are either metal layers or semiconductor layers and in either case are covered with an insulating layer which carries a conductive layer for connection to a high frequency supply.

Inventors

  • 👤 Gerhard Krause

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 23:51
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/082

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 202 words
A circuit arrangement comprising: first, second, third and fourth transistors each including a base, an emitter and a collector, said emitters connected to a common reference potential, said bases of said first and second transistors adapted to receive d.c. logic control signals, said base of said third transistor connected to said collectors of said first and second transistors, said base of said fourth transistor connected to said collector of said third transistor, a resistor, said collector of said fourth transistor serving as an a.c. and d.c. output and connected to a d.c. supply potential via said resistor, and a.c. supply means adapted to receive a high frequency a.c. signal, said supply means connected to said collectors of said first, second and third transistors, blocking of said first and second transistors by said control signals causing conduction of said third transistor to shunt the a.c. signal from said fourth transistor to maintain it blocked and provide a d.c. output via the d.c. supply and said resistor, conduction of either of said first and second transistors shunting the a.c. signal from said third transistor causing conduction of said fourth transistor at the frequency of the a.c. signal to provide a d.c. and a.c. output.
Claim 2
Dependent Claim 202 words
A circuit arrangement comprising: first, second, third and fourth transistors each including a base, an emitter and a collector, said emitters connected to a common reference potential, said bases of said first and second transistors adapted to receive d.c. logic control signals, said base of said third transistor connected to said collectors of said first and second transistors, said base of said fourth transistor connected to said collector of said third transistor, a resistor, said collector of said fourth transistor serving as an a.c. and d.c. output and connected to a d.c. supply potential via said resistor, and a.c. supply means adapted to receive a high frequency a.c. signal, said supply means connected to said collectors of said first, second and third transistors, blocking of said first and second transistors by said control signals causing conduction of said third transistor to shunt the a.c. signal from said fourth transistor to maintain it blocked and provide a d.c. output via the d.c. supply and said resistor, conduction of either of said first and second transistors shunting the a.c. signal from said third transistor causing conduction of said fourth transistor at the frequency of the a.c. signal to provide a d.c. and a.c. output.

References Cited (Backward Citations)

US2962604A Cited
US3383570A Cited
US3715613A Cited
US4004160A Cited
US3911466A Cited
US3953875A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1983-02-25 1983-08-27 1984-02-26 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1987-02-25 1987-08-27 1988-02-26 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1991-02-25 1991-08-27 1992-02-26 $7700.00 Window Closed / Lapsed

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