US4189766A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Racing circuit for controlling access of processor units to a common device
Assignee: NTT Inc
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Filing: 1978-04-12
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Granted: 1980-02-19
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Expires: 1998-04-12
Abstract
Abstract A racing circuit wherein request signals which are asynchronously and simultaneously generated by a plurality of processor units for requesting the use of a common resource such as a memory are temporarily stored, and one of the stored request signals is selected so that the corresponding processor unit may access and use the common resource. The circuit provides a buffer arrangement for causing a first received request signal to lock out other request signals which follow the first signal too closely, and for providing access to the common memory or other device in the order in which access requests were received. The processor unit may control the racing circuit so that the processor unit may attain the exclusive use of the common resource as long as it desires.
Inventors
- 👤 Shinju Horiguchi
- 👤 Joji Sahashi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 23:32
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/16; G06F13/18
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
435 words
A racing circuit for controlling access of a plurality of processor units to a common device, comprising: a request signal memory circuit consisting of a plurality of first pairs of NAND gates, the output terminal of one NAND gate of each pair being connected to one input terminal of the other NAND gate thereof, the output terminal of the other NAND gate of said pair being connected to one input of said one NAND gate thereof, an inhibit signal output NAND gate, the other terminal of said one NAND gate of said pair being connected to the output terminal of said inhibit signal output NAND gate, the input terminals of the inhibit signal output NAND gate being connected to the output terminals of each of said other NAND gates in each of said pairs of NAND gates; a priority selection circuit comprising a plurality of priority selection NAND gates, a corresponding plurality of first inverter circuits, the outputs of each of the pairs of NAND gates of said request signal memory circuit being respectively connected to (i) the input terminals of corresponding priority selection NAND gates through corresponding ones of said first inverter circuits and to (ii) one or more input terminals of another pair of the priority selection NAND gates; an output NAND gate having input terminals connected so the output terminals of said priority selection NAND gates and one output terminal for outputting a request signal; and a selected signal memory circuit comprising a plurality of second pairs of NAND gates, the output terminal of one NAND gate of each of said second pairs being connected to one input terminal of the other NAND gate thereof, the output terminal of the other NAND gate of each of said second pairs being connected to one input of the one NAND gate thereof, the other terminal of the one NAND gate thereof being connected to one of the output terminals of said priority selection circuit, the other terminal of the other NAND gate thereof being connected to a permission signal input terminal, an output of the other NAND gate thereof being connected to one or more of the input terminals of the priority selection NAND gates coupled to each of said first pairs of NAND gates, a plurality of second inverter circuits, each of said second inverter circuits having an input terminal coupled to an output terminal of a corresponding one of said other NAND gates of said first pairs of NAND gates, whereby the output terminals of the other NAND gates of said signal memory circuit output permission signals through said second inverter circuits.
Claim 2
Dependent Claim
435 words
A racing circuit for controlling access of a plurality of processor units to a common device, comprising: a request signal memory circuit consisting of a plurality of first pairs of NAND gates, the output terminal of one NAND gate of each pair being connected to one input terminal of the other NAND gate thereof, the output terminal of the other NAND gate of said pair being connected to one input of said one NAND gate thereof, an inhibit signal output NAND gate, the other terminal of said one NAND gate of said pair being connected to the output terminal of said inhibit signal output NAND gate, the input terminals of the inhibit signal output NAND gate being connected to the output terminals of each of said other NAND gates in each of said pairs of NAND gates; a priority selection circuit comprising a plurality of priority selection NAND gates, a corresponding plurality of first inverter circuits, the outputs of each of the pairs of NAND gates of said request signal memory circuit being respectively connected to (i) the input terminals of corresponding priority selection NAND gates through corresponding ones of said first inverter circuits and to (ii) one or more input terminals of another pair of the priority selection NAND gates; an output NAND gate having input terminals connected so the output terminals of said priority selection NAND gates and one output terminal for outputting a request signal; and a selected signal memory circuit comprising a plurality of second pairs of NAND gates, the output terminal of one NAND gate of each of said second pairs being connected to one input terminal of the other NAND gate thereof, the output terminal of the other NAND gate of each of said second pairs being connected to one input of the one NAND gate thereof, the other terminal of the one NAND gate thereof being connected to one of the output terminals of said priority selection circuit, the other terminal of the other NAND gate thereof being connected to a permission signal input terminal, an output of the other NAND gate thereof being connected to one or more of the input terminals of the priority selection NAND gates coupled to each of said first pairs of NAND gates, a plurality of second inverter circuits, each of said second inverter circuits having an input terminal coupled to an output terminal of a corresponding one of said other NAND gates of said first pairs of NAND gates, whereby the output terminals of the other NAND gates of said signal memory circuit output permission signals through said second inverter circuits.
Claim 3
Dependent Claim
54 words
A racing circuit as set forth in claim 1 wherein the input terminals of said NAND gates of the priority selection circuit are respectively connected to those outputs of the NAND gates of said selected signal memory circuit to which the output of said NAND gates of the priority selection circuit are not connected.
Claim 4
Dependent Claim
20 words
A racing circuit as set forth in claim 1 wherein said inhibit signal output gate consists of a NAND gate.
Claim 5
Dependent Claim
36 words
A racing circuit as set forth in claim 1 wherein said inhibit signal output gate consists of an OR gate the input terminals of which are connected to the output terminals of said first inverter circuit.
Claim 6
Dependent Claim
21 words
A racing circuit as set forth in claim 1 wherein said first and second inverter circuits each consist of NAND gates.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-02-18 | 1983-08-20 | 1984-02-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-02-18 | 1987-08-20 | 1988-02-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-02-18 | 1991-08-20 | 1992-02-19 | $7700.00 | Window Closed / Lapsed |