Fault tolerant bubble memory with redundancy using a stationary register on a single chip

Abstract

Abstract In a field access type bubble memory system using a major loop-minor loop organization, redundant loops are included in each memory chip so that defective minor loops may be disregarded and the memory retain its nominal capacity. Thus, the total number of loops is in excess of the nominal capacity. In one form of the invention the redundant loops are included with the minor loops. In another form of the invention, the redundant loops are independent of the minor loops. A stationary register or flaw chain having at least as many storage locations as the number of minor loops is located on the bubble memory chip with the major and minor loops. Each register location is assigned to contain information with respect to an assigned corresponding minor loop. An appropriate binary code identifies in the appropriate register location the corresponding minor loop which is defective, including nominally defective minor loops, if necessary, so that a number of loops equal to the nominal capacity of the memory are identified as good. Each time the memory is accessed, the contents of the register are accessed, nondestructively, and combined with the contents of the major loop so that only usable minor loops are accessed. Appropriate logic identifies which minor loops are to be accessed for both reading and writing. In one form of the invention, the contents of the stationary register are combined with the output of the major loop by means of a merge network on an alternating basis. In another form of the invention, the major loop is only associated with the nominal capacity number of minor loops and is disabled at the time a defective minor loop data position is to be accessed while at the same time an independent redundant minor loop is separately enabled.

Inventors

• 👤 Clarence H. Kammann

Bibliographic Details