Control panel self-test

Claim 2

Apparatus comprising: means for supplying a first binary address; a computer means; means for transmitting said first binary address to said computer means, said computer means performing a predetermined function in response to said first binary address; a data display means; means for transmitting data from said computer means to said data display means; and means for testing said means for supplying said first binary address and said data display means, said means for testing said means for supplying said first binary address and said data display means including means for bypassing said computer means so as to supply said first binary address to said data display means, said data display means displaying a predetermined response to said first binary address if a malfunction does not occur in said means for supplying said first binary address and said data display means, said data display means displaying a response, other than said predetermined response, to said first binary address if a malfunction does occur in said means for supplying said first binary address or said data display means.

Claim 3

Apparatus in accordance with claim 1 wherein said means for bypassing said computer means so as to supply said first binary address to said data display means comprises: a memory means; a data display driver means; means for writing said first binary address into said memory means on the data input lines of said memory means; and means for reading said first binary address out of said memory means to said display driver means in such a manner that said display driver means drives said data display means in response to said first binary address.

Claim 4

Apparatus in accordance with claim 2 wherein said means for testing said means for supplying said first binary address and said data display means additionally comprises: means for generating a timing signal to be utilized as a clock pulse; binary counter means; means for transmitting said timing signal to said binary counter means; means for transmitting a second binary address, generated by said binary counter means in response to said timing signal, from said binary counter means to the address inputs of said memory means, said second binary address being utilized to select the memory location of said memory means to which said first binary address will be written; means for placing said memory means in a write cycle in such a manner that said first binary address is written into the memory location, of said memory means, which was selected by said second binary address; means for placing said memory means in a read cycle, after said first binary address has been stored in said memory means, in such a manner that said first binary address is read out of said memory means and is transmitted to said data display driver means, said data display driver means driving said data display means in response to said first binary address.

Claim 5

Apparatus in accordance with claim 3 wherein said means for transmitting said second binary address from said binary counter means to said memory means comprises: a data selector means; means for transmitting said second binary address from said binary counter means to a first input of said data selector means; and means for enabling said data selector means to transfer said second binary address to the address inputs of said memory means, when it is desired to perform said test of said means for supplying a first binary address and said data display means.

Claim 6

Apparatus in accordance with claim 4 additionally comprising means for transmitting a third binary address from said computer means to a second input of said data selector means, said third binary address being transmitted to the address inputs of said memory means when said test, of said means for supplying a first binary address and said data display means, is not being performed.

Claim 7

Apparatus in accordance with claim 5 wherein said means for supplying said first binary address is a keyboard means.

Claim 8

Apparatus in accordance with claim 6 wherein said first binary address is transmitted from said keyboard means in response to the depressing of a key on said keyboard means; and said first binary address is written into said memory means in response to the depressing of said key on said keyboard means.

Claim 9

Apparatus in accordance with claim 7 wherein said memory means is a random access memory means.

Claim 10

Apparatus in accordance with claim 8 wherein said display means is an alphanumeric display.

Claim 11

Apparatus in accordance with claim 9 wherein said display means is at least one light emitting diode.

Claim 14

A method in accordance with claim 11 wherein said step of bypassing said computer means so as to supply said first binary address to said data display means comprises: writing said first binary address into memory; reading said first binary address out of said memory; and driving said data display means in response to said first binary address which was read out of said memory.

Claim 15

A method in accordance with claim 12 wherein said step of writing said first binary address into said memory comprises: transmitting said first binary address to the data inputs of said memory; generating a timing signal to be utilized as a clock pulse; transmitting a second binary address, generated in response to said timing signal, to the address inputs of said memory, said second binary address being utilized to select the memory location, in said memory, to which said first binary address will be written; and enabling said memory so that said first binary address is written into the memory location, in said memory, selected by said second binary address.

Claim 16

A method in accordance with claim 13 wherein said step of transmitting said second binary address to said address inputs of said memory comprises: generating a third binary address, said third binary address being available to be transmitted to said address inputs of said memory; and enabling the selection of said second binary address to be transmitted to said address inputs of said memory when it is desired to perform said test of said means for supplying a first binary address and said data display means.