Solid state current limiter

Claim 2

A solid state current limiter comprising a substrate of semiconductor material having a plurality of active spot regions each of a diameter within an order of magnitude of 100 microns formed therein separated by an inactive region, said active spot regions having a total cumulative area of at least 0.002 square centimeters, said active spot regions forming conduction channels through which a limited amount of current flows upon application across said substrate of an electric field above a predetermined magnitude, said inactive region serving a block current flow therethrough and to act as a heat sink around each of said active spot regions.

Claim 3

The current limiter according to claim 1 wherein the amount of current flow through said conduction channels increases with increasing magnitudes of applied electric field across said substrate until said predetermined magnitude is reached, whereafter the amount of current flow through said conduction channels is limited by scattering limited velocity effect, said conduction channels remaining open with no field effect pinch-off thereof.

Claim 4

The current limiter according to claim 2 wherein said active spot regions are lightly doped such that the effect of carrier-lattice collisions is significant.

Claim 5

The current limiter according to claim 3 wherein said substrate is of one conductivity type and wherein said inactive region comprises a perforated layer in said substrate, said conduction channels being portions of said substrate extending through the perforations in said layer.

Claim 6

The current limiter according to claim 4 wherein said perforated layer is of opposite conductivity type.

Claim 7

The current limiter according to claim 5 wherein said perforated layer is formed on a facing surface of said substrate whereby said active spot regions are on said facing surface and are surrounded and separated by said inactive region, the junction between said layer and said substrate blocking one direction of current flow through said layer.

Claim 8

The current limiter according to claim 6 wherein said layer is formed in said substrate by a single diffusion.

Claim 9

The current limiter according to claim 5 wherein said layer is buried in said substrate whereby to afford bipolar operation of said current limiter.

Claim 10

The current limiter according to claim 4 wherein said perforated layer comprises dielectric material.

Claim 11

The current limiter according to claim 1 wherein said active spot regions are spaced at least one diameter apart whereby the average power density along said current limiter is maintained at a moderate level by the heat sinking action of said inactive region despite the localized high power density at said active spot regions, whereby there is afforded in a single chip adequate heat sink means and a usable amount of current flow for practical applications.

Claim 12

A solid state current limiter comprising a substrate of semiconductor material of one conductivity type having at least 20 active spot regions of said one conductivity type each of a diameter of at least 100 microns formed therein separated by an inactive region of opposite conductivity type, said active spot regions forming conduction channels through which a limited amount of current flows upon application across said substrate of an electric field above a predetermined magnitude, the width of each said active spot region being greater than the maximum width of the depletion zones induced thereby by high values of said applied electric field to thus maintain a finite channel width and prevent field effect pinch-off thereof, said inactive region serving to block current flow therethrough and to act as a heat sink around each of said active spot regions.

Claim 13

A solid state current limiter comprising a substrate of semiconductor material of one conductivity type having at least 20 active spot regions of said one conductivity type each of a diameter of at least 100 microns formed therein separated by an inactive region of opposite conductivity type, said active spot regions forming conduction channels through which a limited amount of current flows upon application across said substrate of an electric field above a predetermined magnitude, the width of each said active spot region being greater than the maximum width of the depletion zones induced thereby by high values of said applied electric field to thus maintain a finite channel width and prevent field effect pinch-off thereof, said inactive region serving to block current flow therethrough and to act as a heat sink around each of said active spot regions.

Claim 14

A solid state current limiter comprising a substrate of semiconductor material having greater than about 100 active spot regions each of a width greater than about 50 microns formed therein separated by an inactive region, said active spot regions forming conduction channels through which a limited amount of current flows upon application across said substrate of an electric field above a predetermined magnitude said inactive region serving to block current flow therethrough and to act as a heat sink around each of said active spot regions.

Claim 15

A solid state current limiter comprising a substrate of semiconductor material having greater than about 100 active spot regions each of a width greater than about 50 microns formed therein separated by an inactive region, said active spot regions forming conduction channels through which a limited amount of current flows upon application across said substrate of an electric field above a predetermined magnitude said inactive region serving to block current flow therethrough and to act as a heat sink around each of said active spot regions.

Claim 16

The invention according to claim 12 wherein said current limiter has greater than about 200 said active spot regions each of a width greater than about 100 microns.

Claim 17

A solid state current limiter comprising a substrate of semiconductor material having at least 20 active spot regions each of a diameter of at least 100 microns formed therein separated by an inactive dielectric region, said active spot regions forming conduction channels through which a limited amount of current flows upon application across said substrate of an electric field above a predetermined magnitude, said dielectric region minimizing the formation of depletion zones in said active spot regions even at high values of said applied electric field thus maintaining conduction channel widths substantially equal to active spot widths whereby to prevent field effect pinch-off thereof, said inactive dielectric region serving to block current flow therethrough and to act as a heat sink around each of said active spot regions.

Claim 18

A solid state current limiter comprising a substrate of semiconductor material having at least 20 active spot regions each of a diameter of at least 100 microns formed therein separated by an inactive dielectric region, said active spot regions forming conduction channels through which a limited amount of current flows upon application across said substrate of an electric field above a predetermined magnitude, said dielectric region minimizing the formation of depletion zones in said active spot regions even at high values of said applied electric field thus maintaining conduction channel widths substantially equal to active spot widths whereby to prevent field effect pinch-off thereof, said inactive dielectric region serving to block current flow therethrough and to act as a heat sink around each of said active spot regions.