Patent US2090252A successfully refreshed from Google Patents.
Patent US4186343A successfully refreshed from Google Patents.
US4186343A
Expired / Lapsed
US
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Synchronous frequency synthesis method for a radio trnsmitter-receiver
Assignee: Cybernet Electronics Corp
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Filing: 1977-05-03
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Granted: 1980-01-29
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Expires: 1997-05-03
Abstract
Abstract A synchronous frequency synthesis method for a radio transmitter-receiver, having the steps of applying the reference frequency of a fixed-frequency oscillator to a fixed frequency divider and to a second mixer for converting the reference frequency into a second intermediate frequency of the receiving stage, dividing the controlled frequency of a voltage-controlled oscillator by a variable frequency divider, multiplying the controlled frequency to produce a transmitting carrier frequency, applying the controlled frequency to the first mixer of the receiving stage, applying the divided frequency of the fixed frequency divider to a phase detector so as to produce comparison frequencies, inputting either one of the two frequency division step numbers, obtained from the controlled frequencies for transmission and reception and the comparison frequencies, to a shift-applying code converter adapted to convert the difference between the two frequency division step numbers into the sum of or difference between itself and either one of the two frequency division step numbers thereby generating a command code for the variable frequency divider.
Inventors
- 👤 Takao Kakigi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 15:12
CPC Classifications
H; H04; H04B; H04B1/00; H04B1/38; H04B1/40; H04B1/403; H04B1/405; H03; H03L; H03L7/00; H03L7/06; H03L7/16; H03L7/18; H03L7/183
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
308 words
A synchronous frequency synthesis method for a radio transmitter receiver having a double superheterodyne receiving stage, which comprises the steps of: applying a reference frequency outputted from a fixed-frequency oscillator to a fixed frequency divider and to a second mixer for converting said reference frequency into a second intermediate frequency of said double superheterodyne receiving stage, dividing down a controlled frequency outputted from a voltage-controlled oscillator by a variable frequency divider, feeding said divided-down controlled frequency to a phase detector, multiplying said controlled frequency to produce a transmitting carrier frequency, applying said controlled frequency to a first mixer of said double superheterodyne receiving stage for converting said controlled frequency into a first intermediate frequency of said double superheterodyne receiving stage, applying a divided frequency outputted from said fixed frequency divider as a first comparison frequency directly to the phase detector in each reception period to produce an error signal to alter the output of the voltage-controlled oscillator, said first comparison frequency being equal to the frequency of the voltage-controlled oscillator at the time of reception divided by a first frequency division step number and through another frequency divider as a second comparison frequency to the phase detector during each transmission period to produce an error signal to alter the output of the voltage-controlled oscillator, said second comparison frequency being equal to the frequency of the voltage-controlled oscillator at the time of transmission divided by a second frequency division step number, and inputting one of the two frequency division step numbers to a shift-applying code coverter to increase the one of the two frequency division step numbers by a value equal to the difference between said two frequency division step numbers so as to obtain the other of the two frequency division step numbers, and feed the resulting step number as a command code to said variable frequency divider.
Claim 2
Dependent Claim
308 words
A synchronous frequency synthesis method for a radio transmitter receiver having a double superheterodyne receiving stage, which comprises the steps of: applying a reference frequency outputted from a fixed-frequency oscillator to a fixed frequency divider and to a second mixer for converting said reference frequency into a second intermediate frequency of said double superheterodyne receiving stage, dividing down a controlled frequency outputted from a voltage-controlled oscillator by a variable frequency divider, feeding said divided-down controlled frequency to a phase detector, multiplying said controlled frequency to produce a transmitting carrier frequency, applying said controlled frequency to a first mixer of said double superheterodyne receiving stage for converting said controlled frequency into a first intermediate frequency of said double superheterodyne receiving stage, applying a divided frequency outputted from said fixed frequency divider as a first comparison frequency directly to the phase detector in each reception period to produce an error signal to alter the output of the voltage-controlled oscillator, said first comparison frequency being equal to the frequency of the voltage-controlled oscillator at the time of reception divided by a first frequency division step number and through another frequency divider as a second comparison frequency to the phase detector during each transmission period to produce an error signal to alter the output of the voltage-controlled oscillator, said second comparison frequency being equal to the frequency of the voltage-controlled oscillator at the time of transmission divided by a second frequency division step number, and inputting one of the two frequency division step numbers to a shift-applying code coverter to increase the one of the two frequency division step numbers by a value equal to the difference between said two frequency division step numbers so as to obtain the other of the two frequency division step numbers, and feed the resulting step number as a command code to said variable frequency divider.
Claim 3
Dependent Claim
306 words
A synchronous frequency synthesis method for a radio transmitter receiver having a double superheterodyne receiving stage, which comprises the steps of: applying a reference frequency outputted from a fixed-frequency oscillator to a fixed frequency divider and to a second mixer for converting said reference frequency into a second intermediate frequency of said double superheterodyne receiving stage, dividing down a controlled frequency outputted from a voltage-controlled oscillator by a variable frequency divider, feeding said divided-down controlled frequency to a phase detector, multiplying said controlled frequency to produce a transmitting carrier frequency, applying said controlled frequency to a first mixer of said double superheterodhyne receiving stage for converting said controlled frequency into a first intermediate frequency of said double superheterodyne receiving stage, applying a divided frequency outputted from said fixed frequency divider as a first comparison frequency directly to the phase detector in each reception period to produce an error signal to alter the output of the voltage-controlled oscillator, said first comparison frequency being equal to the frequency of the voltage-controlled oscillator at the time of reception divided by a first frequency division step number and through another frequency divider as a second comparison frequency to the phase detector during each transmission period to produce an error signal to alter the output of the voltage-controlled oscillator, said second comparison frequency being equal to the frequency of the voltage-controlled oscillator at the time of transmission divided by a second frequency division step number, and inputting one of the two frequency division step numbers to a shift-applying code converter to decrease the one of the two frequency division step numbers by a value equal to the difference between the two step numbers so as to obtain the other of the two frequency division step numbers, and feed the resulting step number as a command code to said variable frequency divider.
Claim 4
Dependent Claim
306 words
A synchronous frequency synthesis method for a radio transmitter receiver having a double superheterodyne receiving stage, which comprises the steps of: applying a reference frequency outputted from a fixed-frequency oscillator to a fixed frequency divider and to a second mixer for converting said reference frequency into a second intermediate frequency of said double superheterodyne receiving stage, dividing down a controlled frequency outputted from a voltage-controlled oscillator by a variable frequency divider, feeding said divided-down controlled frequency to a phase detector, multiplying said controlled frequency to produce a transmitting carrier frequency, applying said controlled frequency to a first mixer of said double superheterodhyne receiving stage for converting said controlled frequency into a first intermediate frequency of said double superheterodyne receiving stage, applying a divided frequency outputted from said fixed frequency divider as a first comparison frequency directly to the phase detector in each reception period to produce an error signal to alter the output of the voltage-controlled oscillator, said first comparison frequency being equal to the frequency of the voltage-controlled oscillator at the time of reception divided by a first frequency division step number and through another frequency divider as a second comparison frequency to the phase detector during each transmission period to produce an error signal to alter the output of the voltage-controlled oscillator, said second comparison frequency being equal to the frequency of the voltage-controlled oscillator at the time of transmission divided by a second frequency division step number, and inputting one of the two frequency division step numbers to a shift-applying code converter to decrease the one of the two frequency division step numbers by a value equal to the difference between the two step numbers so as to obtain the other of the two frequency division step numbers, and feed the resulting step number as a command code to said variable frequency divider.
Claim 5
Dependent Claim
304 words
A synchronous frequency synthesis method for a radio transmitter receiver having a double superheterodyne receiving stage, which comprises the steps of: applying a reference frequency outputted from a fixed-frequency oscillator to a fixed frequency divider and to a second mixer for converting said reference frequency into a second intermediate frequency of said double superheterodyne receiving stage, dividing down a controlled frequency outputted from a voltage-controlled oscillator by a variable frequency divider, feeding said divided-down controlled frequency to a phase detector, multiplying said controlled frequency to produce a transmitting carrier frequency, applying said controlled frequency to a first mixer of said double superheterodyne receiving stage for converting said controlled frequency into a first intermediate frequency of said double superheterodyne receiving stage, applying a divided frequency outputted from said fixed frequency divider as a first comparison frequency directly to the phase detector in each reception period to produce an error signal to alter the output of the voltage-controlled oscillator, said first comparison frequency being equal to the frequency of the voltage-controlled oscillator at the time of reception divided by a first frequency division step number and as a second comparison frequency to the phase detector during each transmission period to produce an error signal to alter the output of the voltage-controlled oscillator, said second comparison frequency being equal to the frequency of the voltage-controlled oscillator at the time of transmission divided by a second frequency division step number, and inputting one of the two frequency division step numbers to a shift-applying code converter to increase the one of the two frequency division step numbers by a value equal to the difference between said two frequency division step numbers so as to obtain the other of the two frequency division step numbers, and feed the resulting step number as a command code to said variable frequency divider.
Claim 6
Dependent Claim
304 words
A synchronous frequency synthesis method for a radio transmitter receiver having a double superheterodyne receiving stage, which comprises the steps of: applying a reference frequency outputted from a fixed-frequency oscillator to a fixed frequency divider and to a second mixer for converting said reference frequency into a second intermediate frequency of said double superheterodyne receiving stage, dividing down a controlled frequency outputted from a voltage-controlled oscillator by a variable frequency divider, feeding said divided-down controlled frequency to a phase detector, multiplying said controlled frequency to produce a transmitting carrier frequency, applying said controlled frequency to a first mixer of said double superheterodyne receiving stage for converting said controlled frequency into a first intermediate frequency of said double superheterodyne receiving stage, applying a divided frequency outputted from said fixed frequency divider as a first comparison frequency directly to the phase detector in each reception period to produce an error signal to alter the output of the voltage-controlled oscillator, said first comparison frequency being equal to the frequency of the voltage-controlled oscillator at the time of reception divided by a first frequency division step number and as a second comparison frequency to the phase detector during each transmission period to produce an error signal to alter the output of the voltage-controlled oscillator, said second comparison frequency being equal to the frequency of the voltage-controlled oscillator at the time of transmission divided by a second frequency division step number, and inputting one of the two frequency division step numbers to a shift-applying code converter to increase the one of the two frequency division step numbers by a value equal to the difference between said two frequency division step numbers so as to obtain the other of the two frequency division step numbers, and feed the resulting step number as a command code to said variable frequency divider.
Claim 7
Dependent Claim
302 words
A synchronous frequency synthesis method for a radio transmitter receiver having a double superheterodyne receiving stage, which comprises the steps of: applying a reference frequency outputted from a fixed-frequency oscillator to a fixed frequency divider and to a second mixer for converting said reference frequency into a second intermediate frequency of said double superheterodyne receiving stage, dividing down a controlled frequency outputted from a voltage-controlled oscillator by a variable frequency divider, feeding said divided-down controlled frequency to a phase detector, multiplying said controlled frequency to produce a transmitting carrier frequency, applying said controlled frequency to a first mixer of said double superheterodyne receiving stage for converting said controlled frequency into a first intermediate frequency of said double superheterodyne receiving stage, applying a divided frequency outputted from said fixed frequency divider as a first comparison frequency directly to the phase detector in each reception period to produce an error signal to alter the output of the voltage-controlled oscillator, said first comparison frequency being equal to the frequency of the voltage-controlled oscillator at the time of reception divided by a first frequency division step number and as a second comparison frequency to the phase detector during each transmission period to produce an error signal to alter the output of the voltage-controlled oscillator, said second comparison frequency being equal to the frequency of the voltage-controlled oscillator at the time of transmission divided by a second frequency division step number, and inputting one of the two frequency division step numbers to a shift-applying code converter to decrease the one of the two frequency division step numbers by a value equal to the difference between the two step numbers so as to obtain the other of the two frequency division step numbers, and feed the resulting step number as a command code to said variable frequency divider.
Claim 8
Dependent Claim
302 words
A synchronous frequency synthesis method for a radio transmitter receiver having a double superheterodyne receiving stage, which comprises the steps of: applying a reference frequency outputted from a fixed-frequency oscillator to a fixed frequency divider and to a second mixer for converting said reference frequency into a second intermediate frequency of said double superheterodyne receiving stage, dividing down a controlled frequency outputted from a voltage-controlled oscillator by a variable frequency divider, feeding said divided-down controlled frequency to a phase detector, multiplying said controlled frequency to produce a transmitting carrier frequency, applying said controlled frequency to a first mixer of said double superheterodyne receiving stage for converting said controlled frequency into a first intermediate frequency of said double superheterodyne receiving stage, applying a divided frequency outputted from said fixed frequency divider as a first comparison frequency directly to the phase detector in each reception period to produce an error signal to alter the output of the voltage-controlled oscillator, said first comparison frequency being equal to the frequency of the voltage-controlled oscillator at the time of reception divided by a first frequency division step number and as a second comparison frequency to the phase detector during each transmission period to produce an error signal to alter the output of the voltage-controlled oscillator, said second comparison frequency being equal to the frequency of the voltage-controlled oscillator at the time of transmission divided by a second frequency division step number, and inputting one of the two frequency division step numbers to a shift-applying code converter to decrease the one of the two frequency division step numbers by a value equal to the difference between the two step numbers so as to obtain the other of the two frequency division step numbers, and feed the resulting step number as a command code to said variable frequency divider.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-01-28 | 1983-07-30 | 1984-01-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-01-28 | 1987-07-30 | 1988-01-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-01-28 | 1991-07-30 | 1992-01-29 | $7700.00 | Window Closed / Lapsed |