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US4185453A Expired / Lapsed US ⏱️ 0.0 years remaining

Time setting and correcting circuit for electronic timepieces

Assignee: SSIH Management Services SA
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Filing: 1977-10-17
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Granted: 1980-01-29
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Expires: 1997-10-17
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Abstract

Abstract A time setting and correction circuit is provided for a quartz time stand timepiece in which the use of memory circuits permits the correction of minute hand setting, hour hand setting and internal putting into phase of seconds through actuation of a single switch.

Inventors

  • 👤 Jean-Pierre Jaunin

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 18:39
CPC Classifications
G; G04; G04G; G04G5/00; G04G5/02; G04C; G04C9/00

Claims Analysis

Total Claims: 11
Claim 1
Independent Claim 192 words
In an electronic timepiece having a quartz crystal time standard, a stepping motor for applying driving motion to coupled minute and hour indicating hands, and multistage frequency dividing means responsive to signals from said time standard for applying stepping signals at a predetermined first frequency to said stepping motor, the improvement comprising a time setting and correcting circuit including: a single user-actuable switch; a first memory means; timing means responsive to said switch for setting said first memory means after actuation of said switch for a predetermined interval of time; circuit means responsive to said frequency dividing means and said first memory means for applying supplemental stepping signals to said motor at a second frequency higher than said first frequency; counter means connected to said first memory means and said frequency dividing means for counting said supplemental signals of said second frequency, said counter having an output connected to reset said first memory means when said counter means reaches a predetermined count; and, means responsive to said switch for applying at least one supplemental stepping signal to said motor upon actuation of said switch for less than said predetermined interval of time.
Claim 2
Dependent Claim 192 words
In an electronic timepiece having a quartz crystal time standard, a stepping motor for applying driving motion to coupled minute and hour indicating hands, and multistage frequency dividing means responsive to signals from said time standard for applying stepping signals at a predetermined first frequency to said stepping motor, the improvement comprising a time setting and correcting circuit including: a single user-actuable switch; a first memory means; timing means responsive to said switch for setting said first memory means after actuation of said switch for a predetermined interval of time; circuit means responsive to said frequency dividing means and said first memory means for applying supplemental stepping signals to said motor at a second frequency higher than said first frequency; counter means connected to said first memory means and said frequency dividing means for counting said supplemental signals of said second frequency, said counter having an output connected to reset said first memory means when said counter means reaches a predetermined count; and, means responsive to said switch for applying at least one supplemental stepping signal to said motor upon actuation of said switch for less than said predetermined interval of time.
Claim 3
Dependent Claim 16 words
The improvement as claimed in claim 1 wherein said counter means comprises a modulo 60 counter.
Claim 4
Dependent Claim 30 words
The improvement as claimed in claim 1 wherein said frequency dividing means comprises means for applying stepping signals to said stepping motor at a first predetermined frequency of 1/60 Hz.
Claim 5
Dependent Claim 32 words
The improvement as claimed in claim 1 and further comprising means responsive to said first memory means for inhibiting said means for applying at least one supplemental stepping signal to said motor.
Claim 6
Dependent Claim 58 words
The improvement as claimed in claim 1 wherein said means for applying at least one supplemental stepping signal to said motor includes a gating means connected to the output of the last stage of said multistage frequency dividing means for inhibiting said single supplemental stepping signal when said last stage indicates the timepiece is a few seconds fast.
Claim 7
Dependent Claim 32 words
The improvement as claimed in claim 5 and further including means, responsive to said means for applying at least one supplemental signal, for resetting the stages of said multistage frequency dividing means.
Claim 8
Dependent Claim 104 words
The improvement as claimed in claim 1 wherein said means for applying at least one supplemental signal comprises means for applying a single supplemental stepping signal to said motor and includes: second memory means settable in response to each actuation of said switch; means responsive to said first memory means, when set, for resetting said second memory means; third memory means; first gating means connected to said second memory means and said switch for setting said third memory means; and, second gating means connected to said first gating means and said third memory means for applying said single supplemental stepping signal to said motor.
Claim 9
Dependent Claim 51 words
The improvement as claimed in claim 7 wherein said second gating means includes means responsive to said third memory means and said first gating means for generating a single supplemental stepping signal each time said switch is actuated for less than said predetermined interval while said third memory means is set.
Claim 10
Dependent Claim 27 words
The improvement as claimed in claim 7 and further comprising means responsive to said first gating means for resetting the stages of said multistage frequency dividing means.
Claim 11
Dependent Claim 59 words
The improvement as claimed in claim 9 and further including means connecting the last stage of said multistage frequency dividing means to said second gating means, said second gating means being responsive to said third memory means, when set, and a signal from said last stage indicating that the timepiece is slow, to generate said single supplemental stepping signal.

References Cited (Backward Citations)

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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1983-01-28 1983-07-30 1984-01-29 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1987-01-28 1987-07-30 1988-01-29 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1991-01-28 1991-07-30 1992-01-29 $7700.00 Window Closed / Lapsed

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