Time adjusting system for an electronic timepiece

Claim 1

A time adjusting system for an electronic timepiece comprising: an oscillator circuit for generating high frequency pulses; a dividing circuit connected to said oscillator circuit for dividing the high frequency pulses therefrom into 1 HZ pulses for use as time standard pulses and higher frequency pulses higher in frequency than 1 HZ for use as time adjusting pulses; a time-measuring device for measuring time in response to the 1 HZ pulses; a first counter for selectively counting 30 1 HZ pulses from said dividing circuit and providing a corresponding count signal; a discriminating circuit for discriminating between an advanced signal appearing during the first 30 seconds of 1 minute and a delayed signal appearing during the latter 30 seconds of the 1 minute in response to the count signal provided by said first counter; a second counter comprising an up-down 30-counter for counting 1 HZ pulses when counting in an up-counting mode; a first gate circuit connected to said dividing circuit to receive therefrom the 1 HZ pulses and the higher frequency pulses operative to selectively apply them to said time-measuring device and operative to selectively apply the 1 HZ pulses to said first counter; a second gate circuit connected to said dividing circuit to receive therefrom the 1 HZ pulses and the higher frequency pulse and operative to selectively apply them to said second counter; a manually operable switch operable to initiate the time adjustment; control circuit means responsive to operation of said switch for generating a control signal and applying it to said first gate circuit which responds thereto to stop the supply of 1 HZ pulses and higher frequency pulses to said time-measuring device and to stop the supply of the 1 HZ pulses to said first counter, and applying the control signal to said second gate circuit which responds thereto to supply 1 HZ pulses to said second counter and for changing the operation of said second counter to the down-counting mode when said advanced signal is generated from said discriminating circuit, and applying the control signal to said first gate circuit and second gate circuit which respond thereto to supply the higher frequency pulses to said time-measuring device and second counter when said delayed signal is generated from said discriminating circuit; a pre-setting circuit for presetting the counting content of said first counter in said second counter when operating in the down-counting mode when the counting content reaches 0-second in response to the control signal; and a resetting circuit for resetting said control circuit when the counting content of said second counter reaches 0-second when operating in the down-counting mode in response to the control signal, and for resetting said control circuit, first counter and discriminating circuit when the counting content of said second counter reaches 30-seconds when operating in the up-counting mode.