Abstract Spurious frequencies are eliminated in a direct frequency synthesizer by means of a feed forward correction circuit. The improved direct frequency synthesizer of the invention includes a series adder, clocked register, a D/A converter and a phase corrector. The adder is inputted by a digital control increment and the output of the register. The system clock frequency is divided down by a smoothing counter that in part controls the phase of the output signal. Spurious frequencies are manifested by overflow of the register. The register overflow is converted to an analog signal by the D/A converter. The system output is provided by a voltage controlled oscillator that is controlled by an amplifier which is responsive to both the smoothing counter output and the analog output of the D/A converter. Additionally, the D/A converter is sampled twice for every cycle of output frequency, resulting in a doubling of the output frequency for a given D/A converter.
In a direct frequency synthesizer having a system clock, an adder, a register and a divider, the divider and the register being fed by the system clock and said adder, and the adder being fed by a digital control increment and said register, the improvement residing in a spurious frequency rejection circuit, said spurious frequency rejection circuit comprising a digital to analog converter, a summing means, an amplifier, and a voltage controlled oscillator, said voltage controlled oscillator having an output and being controlled by said amplifier, the output of said voltage controlled oscillator being summed within the output of said divider by said summing means, said amplifier being connected to receive and being responsive to the summed output of said summing means and the output of said digital to analog converter.
Claim 2
Dependent Claim
131 words
In a direct frequency synthesizer having a system clock, an adder, a register and a divider, the divider and the register being fed by the system clock and said adder, and the adder being fed by a digital control increment and said register, the improvement residing in a spurious frequency rejection circuit, said spurious frequency rejection circuit comprising a digital to analog converter, a summing means, an amplifier, and a voltage controlled oscillator, said voltage controlled oscillator having an output and being controlled by said amplifier, the output of said voltage controlled oscillator being summed within the output of said divider by said summing means, said amplifier being connected to receive and being responsive to the summed output of said summing means and the output of said digital to analog converter.
Claim 3
Dependent Claim
27 words
A spurious frequency rejection circuit as defined in claim 1 including a second divider for dividing by 2 the summing means input from the frequency synthesizer divider.