Level shifting circuit

Claim 1

In combination: a first terminal for receiving a reference potential; a second terminal for receiving a bias potential; a third terminal for receiving an input signal swinging over a range bounded by a voltage substantially equal to said reference potential and a voltage remote from said reference potential in the same sense said bias potential is, but in a larger amount; first and second transistors of a first conductivity type and a third transistor of a second conductivity type opposite to said first conductivity type, each of said transistors having respective base and emitter and collector electrodes and having respective emitter-base and collector-base junctions, the collector and base electrodes of said second transistor having respective connections to said first terminal and to said second terminal, with said first conductivity type being such these connections reverse-bias the collector-base junction of said second transistor, the collector electrode of said first transistor being connected to the base electrode of said third transistor, and the emitter electrode of said third transistor being connected to said first terminal; first current source means supplying current to an interconnection between the emitter electrodes of said first and second transistors, which current is of a polarity for forward-biasing at least one of their emitter-base junctions; second current source means supplying a current of like polarity to a node at the collector electrode of said third transistor; resistive means connecting said third terminal to the base electrode of said first transistor and having a sufficiently large resistance that when said input signal swings to said voltage substantially equal to said reference potential, that portion of the current from said first current source means flowing through the emitter-base junction of said first transistor and said resistive means causes a sufficiently large potential drop across said resistive means that transistor action is maintained in said first transistor, permitting a substantial remaining portion of the current from said first current source means to flow through the emitter-base junction of said third transistor, thereby placing said third transistor in conduction to conduct, as collector current, the current applied from said second source means away from the node at its collector electrode; and load means connected to the node at the collector electrode of said third transistor for conducting away such of the current from said second current source means as does not flow as collector current through the collector electrode of said third transistor.