Patent US4183016A successfully refreshed from Google Patents.
US4183016A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Parallel analog-to-digital converter with increased resolution
Assignee: Sony Corp
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Filing: 1978-09-08
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Granted: 1980-01-08
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Expires: 1998-09-08
Abstract
Abstract An analog-to-digital converter of the type including a sample-and-hold circuit for sampling an analog signal during predetermined cycles to produce periodically sampled voltages, a source of reference voltages for supplying plural quantizing voltages having a quantizing voltage step DELTA V, a plurality of voltage comparators for receiving each sampled voltage and the plural quantizing voltages to compare the sampled voltage to respective ones of the quantizing voltage for determining the level of the sampled voltage relative to the quantizing voltages, and an encoder responsive to the voltage comparators to produce a plural-bit code as a function of the determined sampled voltage level. The analog-to-digital converter includes the improvement comprised of an offset supply operative to shift either the sampled voltage level or the quantizing voltages by an offset amount during each sampling cycle, a detector coupled to receive the least significant bit in the plural-bit code produced by the encoder for detecting whether this least significant bit changes in response to the operation of the offset voltage source, and an output circuit for deriving an output digital signal formed of the plural-bit code produced by the encoder and an additional bit derived from the detector.
Inventors
- 👤 Kiyoshi Sawagata
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 21:24
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/12; H03M1/20; H03M1/202; H03M1/14; H03M1/145; H03M1/146
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
180 words
An analog-to-digital converter comprising sample-and-hold means for sampling an analog signal during predetermined sampling cycles to produce periodically sampled voltages; reference voltage supply means for supplying plural quantizing voltages having a quantizing voltage step ΔV; a plurality of voltage comparators for receiving each sampled voltage and said plural quantizing voltages to compare said sampled voltage to each of said quantizing voltages for determining the level of said sampled voltage relative to said quantizing voltages; encoding means responsive to said voltage comparators to produce a plural-bit code as a function of the determined sampled voltage level; offset voltage supply means operative to shift the sampled voltage level relative to said quantizing voltages during each sampling cycle; detecting means coupled to receive the least significant bit in said plural-bit code produced by said encoding means for detecting whether said least significant bit changes in response to the operation of said offset voltage supply means; and output means for deriving an output digital signal formed of said plural-bit code produced by said encoding means and an additional bit derived from said detecting means.
Claim 2
Dependent Claim
180 words
An analog-to-digital converter comprising sample-and-hold means for sampling an analog signal during predetermined sampling cycles to produce periodically sampled voltages; reference voltage supply means for supplying plural quantizing voltages having a quantizing voltage step ΔV; a plurality of voltage comparators for receiving each sampled voltage and said plural quantizing voltages to compare said sampled voltage to each of said quantizing voltages for determining the level of said sampled voltage relative to said quantizing voltages; encoding means responsive to said voltage comparators to produce a plural-bit code as a function of the determined sampled voltage level; offset voltage supply means operative to shift the sampled voltage level relative to said quantizing voltages during each sampling cycle; detecting means coupled to receive the least significant bit in said plural-bit code produced by said encoding means for detecting whether said least significant bit changes in response to the operation of said offset voltage supply means; and output means for deriving an output digital signal formed of said plural-bit code produced by said encoding means and an additional bit derived from said detecting means.
Claim 3
Dependent Claim
22 words
The analog-to-digital converter of claim 1, wherein said offset supply means supplies an offset voltage to be superimposed onto said sampled voltage.
Claim 4
Dependent Claim
22 words
The analog-to-digital converter of claim 1, wherein said offset supply means supplies an offset voltage to be superimposed onto said analog signal.
Claim 5
Dependent Claim
29 words
The analog-to-digital converter of claim 1, wherein said offset supply means supplies an offset voltage to be superimposed onto each of said quantizing voltages supplied to said voltage comparators.
Claim 6
Dependent Claim
17 words
The analog-to-digital converter of claim 2, 3 or 4 wherein said offset voltage is equal to ΔV/2.
Claim 7
Dependent Claim
90 words
The analog-to-digital converter of claim 1, wherein said encoding means produces an n-bit code and wherein said output means comprises a first stage of n storage means for storing said n-bit code and a second stage of n+1 storage means for receiving and storing the n-bit bode from said first stage and for receiving and storing an additional bit whose value is a function of whether said least significant bit in the code produced by said encoding means changes in response to said operation of said offset voltage supply means.
Claim 8
Dependent Claim
59 words
The analog-to-digital converter of claim 6 wherein said first stage is comprised of n triggerable flip-flop means coupled to said encoding means: and a source of trigger pulses for triggering said n triggerable flip-flop means in said first stage to store the n-bit code produced by said encoding means prior to the operation of said offset voltage supply means.
Claim 9
Dependent Claim
79 words
The analog-to-digital converter of claim 7 wherein said second stage is comprised of n+1 triggerable flip-flop means, respective ones of which are coupled to said n flip-flop means in said first stage and to said detecting means; and a second source of trigger pulses for triggering said n+1 triggerable flip-flop means in said second stage to store the n-bit code stored in said first stage plus said additional bit subsequent to the operation of said offset voltage supply means.
Claim 10
Dependent Claim
53 words
The analog-to-digital converter of claim 6, 7 or 8 wherein said detecting means comprises an exclusive-OR gate having one input coupled to receive the least significant bit in the code produced by said encoding means and another input coupled to receive the least significant bit in the code stored in said first stage.
References Cited (Backward Citations)
US3656152A
Cited
US3949170A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-01-07 | 1983-07-09 | 1984-01-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-01-07 | 1987-07-09 | 1988-01-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-01-07 | 1991-07-09 | 1992-01-08 | $7700.00 | Window Closed / Lapsed |