US4181941A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Interrupt system and method
Assignee: Texas Instruments Tucson Corp
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Filing: 1978-03-27
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Granted: 1980-01-01
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Expires: 1998-03-27
Abstract
Abstract Method and system for responding to an interrupt signal sent to a microprocessor from one of a plurality of peripheral devices. An acknowledge signal is transmitted from the microprocessor to the peripheral devices. The acknowledge signal operatively isolates select/request terminals of the respective peripheral devices from outputs of a select code decoder. The acknowledge signal also enables the select/request terminals to be inputted to a priority encoder. The acknowledge signal further enables a signal to be produced on the select/request terminal of the interrupting peripheral device, thereby causing the priority encoder to produce a select code representative of the interrupting peripheral device. The select code is subsequently inputted to the microprocessor to enable the microprocessor to access an interrupt service subroutine for the interrupting peripheral device. Subsequent to the end of the acknowledge signal, the select code is inputted by the microprocessor to a select code decoder and is decoded thereby to produce an enable signal which is transmitted to the select/request terminal of the interrupting peripheral device. The enable signal enables the interrupting peripheral device to communicate with the microprocessor via the data bus, thereby permitting the interrupting peripheral device to be serviced by the accessed interrupt service subroutine.
Inventors
- 👤 Ernest E. Godsey
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 06:24
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/24; G06F13/26
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
228 words
A control system comprising in combination: (a) a processor device for executing stored instructions; (b) a plurality of peripheral devices coupled to the processor device by means of a bus; (c) an interrupt conductor connected to said processor device and each of said peripheral devices for conducting interrupt request signals from said peripheral devices, said processor device having means for producing acknowledge information in response to said interrupt request signals; (d) an acknowledge conductor coupled to said processor device and each of said peripheral devices for conducting said acknowledge information to each of said peripheral devices; (e) first means responsive to said acknowledge information and said interrupt request signals for enabling each of said interrupting peripheral devices to transmit a respective encode signal; (f) a plurality of conductor means coupled, respectively, to said plurality of peripheral devices for conducting said encode signals; (g) priority encoding means having a plurality of inputs coupled, respectively, to said conductor means and responsive to said encode signals for producing a code representing the identity of a highest priority one of said interrupting peripheral devices; (h) means responsive to said code for producing a selection signal on the one of said conductor means connected to said highest priority interrupting peripheral device; and (i) second means responsive to said selection signal for enabling said highest priority interrupting peripheral device to communicate with said bus.
Claim 2
Dependent Claim
228 words
A control system comprising in combination: (a) a processor device for executing stored instructions; (b) a plurality of peripheral devices coupled to the processor device by means of a bus; (c) an interrupt conductor connected to said processor device and each of said peripheral devices for conducting interrupt request signals from said peripheral devices, said processor device having means for producing acknowledge information in response to said interrupt request signals; (d) an acknowledge conductor coupled to said processor device and each of said peripheral devices for conducting said acknowledge information to each of said peripheral devices; (e) first means responsive to said acknowledge information and said interrupt request signals for enabling each of said interrupting peripheral devices to transmit a respective encode signal; (f) a plurality of conductor means coupled, respectively, to said plurality of peripheral devices for conducting said encode signals; (g) priority encoding means having a plurality of inputs coupled, respectively, to said conductor means and responsive to said encode signals for producing a code representing the identity of a highest priority one of said interrupting peripheral devices; (h) means responsive to said code for producing a selection signal on the one of said conductor means connected to said highest priority interrupting peripheral device; and (i) second means responsive to said selection signal for enabling said highest priority interrupting peripheral device to communicate with said bus.
Claim 3
Dependent Claim
33 words
The control system of claim 1 further including means responsive to said processor device for decoding said acknowledge information to produce an acknowledge signal and transmitting said acknowledge signal on said acknowledge conductor.
Claim 4
Dependent Claim
13 words
The control system of claim 2 wherein said processor device is a microprocessor.
Claim 5
Dependent Claim
18 words
The control system of claim 3 wherein said microprocessor is a complementary field effect transistor integrated circuit microprocessor.
Claim 6
Dependent Claim
38 words
The control system of claim 4 further including a plurality of buffer circuits responsive to the outputs of said selection signal producing means for electrically decoupling said outputs from said conductor means in response to said acknowledge signal.
Claim 7
Dependent Claim
56 words
The control system of claim 5 wherein said buffer circuits include a plurality of three-state non-inverting buffers, each having an input connected to an output of said selection signal producing means and each having an output connected to a respective one of said conductor means and each having an enable input responsive to said acknowledge signal.
Claim 8
Dependent Claim
29 words
The control system of claim 5 wherein said encoding means includes input enabling means responsive to said acknowledge signal for operatively coupling said conductor means to said encoding means.
Claim 9
Dependent Claim
48 words
The control system of claim 2 further including means for inputting data and selection information into said processor device from a separate control system to effect selection of one of said peripheral devices determined by said selection information and to input said data to said selected peripheral device.
Claim 10
Dependent Claim
21 words
The control system of claim 6 wherein said first means enables said transmitting of said encode signals during said acknowledge signal.
Claim 11
Dependent Claim
24 words
The control system of claim 7 wherein said input enabling means operatively couples said conductor means to said encoding means during said acknowledge signal.
Claim 12
Dependent Claim
29 words
The control system of claim 6 wherein said enable input is responsive to said acknowledge signal to isolate the outputs of said three-state non-inverting buffers during said acknowledge signal.
Claim 13
Dependent Claim
18 words
The control system of claim 1 wherein said first enabling means is incorporated in said interrupting peripheral device.
Claim 14
Dependent Claim
218 words
In a control system including a processor device for executing stored instructions, a plurality of peripheral devices coupled to the processor device by a bus, and an interrupt conductor connected to the processor device and the peripheral devices for conducting interrupt request signals from interrupting ones of the peripheral devices, an interrupt system comprising in combination: (a) first means responsive to an interrupt request signal applied to the interrupting peripheral device by equipment controlled by the control system for enabling each of said interrupting peripheral devices to transmit a respective encode signal to said priority encoding means; (b) priority encoding means responsive to said respective encode signals for producing a select code representing a highest priority interrupting peripheral device; (c) decoding means for decoding said select code to produce a selection signal to select said highest priority interrupting peripheral device; (d) second means responsive to said selection signal for enabling said highest priority interrupting peripheral device to communicate with said processor device via said bus; (e) a plurality of conductor means each coupling a respective one of said peripheral devices to said decoding means and said encoding means for conducting said encode signals from said interrupting peripheral devices to said encoding means and conducting said selection signal from said decoding means to said highest priority interrupting peripheral device.
Claim 15
Dependent Claim
218 words
In a control system including a processor device for executing stored instructions, a plurality of peripheral devices coupled to the processor device by a bus, and an interrupt conductor connected to the processor device and the peripheral devices for conducting interrupt request signals from interrupting ones of the peripheral devices, an interrupt system comprising in combination: (a) first means responsive to an interrupt request signal applied to the interrupting peripheral device by equipment controlled by the control system for enabling each of said interrupting peripheral devices to transmit a respective encode signal to said priority encoding means; (b) priority encoding means responsive to said respective encode signals for producing a select code representing a highest priority interrupting peripheral device; (c) decoding means for decoding said select code to produce a selection signal to select said highest priority interrupting peripheral device; (d) second means responsive to said selection signal for enabling said highest priority interrupting peripheral device to communicate with said processor device via said bus; (e) a plurality of conductor means each coupling a respective one of said peripheral devices to said decoding means and said encoding means for conducting said encode signals from said interrupting peripheral devices to said encoding means and conducting said selection signal from said decoding means to said highest priority interrupting peripheral device.
Claim 16
Dependent Claim
69 words
The interrupt system of claim 13 wherein said first means includes: (a) a microprocessor for sending acknowledge information to each of said peripheral devices in response to said interrupt request signals; and (b) circuit means operating in conjunction with said peripheral devices to enable said interrupting peripheral devices to produce said encode signals in response to said acknowledge information and an interrupt source coupled to said interrupting peripheral devices.
Claim 17
Dependent Claim
70 words
The interrupt system of claim 14 further including: (a) output means coupled to said decoding means for operatively isolating said conductor means from said decoding means in response to said acknowledge information; and (b) input means coupled to said priority encoding means for operatively coupling said conductor means to said priority encoding means in response to said acknowledge information to enable said priority encoding means to receive said encode signals.
Claim 18
Independent Claim
190 words
A method of operating an automatic control system, the automatic control system including a controller, a plurality of peripheral devices coupled to the controller by means of a bus, a priority encoder having inputs connected, respectively, to each of the peripheral devices, said method comprising the steps of: (a) transmitting interrupt request signals from interrupting ones of said peripheral devices to said controller; (b) transmitting an acknowledge message from said controller to each of said peripheral devices in response to said interrupt request signal; (c) transmitting encode signals from each of said interrupting peripheral devices via a plurality of conductors, respectively, to said priority encoder in response to said acknowledge signal and said interrupt signals to cause said priority encoder to generate a code representing the highest priority one of said interrupting peripheral devices; (d) producing a select signal in response to said code; (e) transmitting said select signal to said highest priority interrupting peripheral device via the one of said conductors coupled to said highest priority interrupting peripheral device; and (f) enabling said highest priority interrupting peripheral device to communicate with said bus in response to said select signal.
Claim 19
Independent Claim
190 words
A method of operating an automatic control system, the automatic control system including a controller, a plurality of peripheral devices coupled to the controller by means of a bus, a priority encoder having inputs connected, respectively, to each of the peripheral devices, said method comprising the steps of: (a) transmitting interrupt request signals from interrupting ones of said peripheral devices to said controller; (b) transmitting an acknowledge message from said controller to each of said peripheral devices in response to said interrupt request signal; (c) transmitting encode signals from each of said interrupting peripheral devices via a plurality of conductors, respectively, to said priority encoder in response to said acknowledge signal and said interrupt signals to cause said priority encoder to generate a code representing the highest priority one of said interrupting peripheral devices; (d) producing a select signal in response to said code; (e) transmitting said select signal to said highest priority interrupting peripheral device via the one of said conductors coupled to said highest priority interrupting peripheral device; and (f) enabling said highest priority interrupting peripheral device to communicate with said bus in response to said select signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-12-31 | 1983-07-02 | 1984-01-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-12-31 | 1987-07-02 | 1988-01-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-12-31 | 1991-07-02 | 1992-01-01 | $7700.00 | Window Closed / Lapsed |