Adaptive synchronizing circuit for decoding phase-encoded data

Claim 2

A circuit for providing a blanking pulse comprising: a first means having first and second inputs and an output for producing a first state at said output in response to a first signal at said first input; a second means for producing a second state at said output in response to a predetermined condition at said second input; and circuit means operatively coupling said output with said second input whereby each of said first and second states is maintained at a relatively stable percentage of the time between successive first signals to said first input when the frequency of said first signals varies, with one of said first and second states of said first means providing said blanking pulse; said second means including means for producing an increasing voltage starting with a said first signal; and said circuit means having a voltage reference point therein and a circuit path for producing a falling voltage level at said reference point in response to said first state; and means operatively coupling said reference point with said second input whereby said first means is shifted to said second state when the falling voltage level at said second input equals the rising voltage produced by said second means.

Claim 3

The circuit as claimed in claim 1 in which said circuit means includes a second circuit path for producing a rising voltage level at said reference point when the output of said first means is in said second state.

Claim 4

The circuit as claimed in claim 2 in which said first circuit path and said second circuit path include a common capacitor.

Claim 5

The circuit as claimed in claim 3 in which said circuit path includes a first impedence in series with said common capacitor and said second circuit path includes a second impedence in series with said common capacitor, said first and second resistors having impedence values corresponding to the durations of time in which said output is in said first and second states, respectively.

Claim 6

The circuit as claimed in claim 4 in which said circuit path includes a first transistor which conducts when said first means is in said first state to cause the voltage level at said reference point to fall, and said second circuit path includes a second transistor which conducts when said first means is in said second state to cause the voltage level at said reference point to rise.

Claim 7

The circuit as claimed in claim 5 in which said first means includes a timer and said means operatively coupling said reference point with said second input includes an operational amplifier.

Claim 8

A circuit for decoding a data stream including data bits and non-data flux reversals comprising: input means for receiving said data bits and non-data flux reversals; output means operatively coupled to said input means to output the decoded data stream; and means for producing a blanking pulse for blanking said non-data flux reversals, comprising: a first means having first and second inputs and an output for producing a first state at said output in response to a first signal at said first input, with said first signal being derived from a said data bit at said input means; a second means for producing a second state at said output in response to a pedetermined condition at said second input; and circuit means operatively coupling said output with said second input whereby each of said first and second states is maintained at a relatively stable percentage of the time between successive first signals to said first input when the frequency of said first signals varies, with one of said first and second states of said first means providing said blanking pulse; said second means including means for producing an increasing voltage starting with a said first signal; and said circuit means having a voltage reference point therein and a circuit path for producing a falling voltage level at said reference point in response to said first state; and means operatively coupling said reference point with said second input whereby said first means is shifted to said second state when the falling voltage level at said second input equals the rising voltage produced by said second means.

Claim 9

A circuit for decoding a data stream including data bits and non-data flux reversals comprising: input means for receiving said data bits and non-data flux reversals; output means operatively coupled to said input means to output the decoded data stream; and means for producing a blanking pulse for blanking said non-data flux reversals, comprising: a first means having first and second inputs and an output for producing a first state at said output in response to a first signal at said first input, with said first signal being derived from a said data bit at said input means; a second means for producing a second state at said output in response to a pedetermined condition at said second input; and circuit means operatively coupling said output with said second input whereby each of said first and second states is maintained at a relatively stable percentage of the time between successive first signals to said first input when the frequency of said first signals varies, with one of said first and second states of said first means providing said blanking pulse; said second means including means for producing an increasing voltage starting with a said first signal; and said circuit means having a voltage reference point therein and a circuit path for producing a falling voltage level at said reference point in response to said first state; and means operatively coupling said reference point with said second input whereby said first means is shifted to said second state when the falling voltage level at said second input equals the rising voltage produced by said second means.

Claim 10

The circuit as claimed in claim 7 in which said circuit means includes a second circuit path for producing a rising voltage level at said reference point when the output of said first means is in said second state.

Claim 11

The circuit as claimed in claim 8 in which said circuit path and said second circuit path include a common capacitor.

Claim 12

The circuit as claimed in claim 9 in which said circuit path includes a first resistor in series with said common capacitor and said second circuit path includes a second resistor in series with said common capacitor, said first and second resistors having resistance values corresponding to the durations of time in which said output is in said first and second states, respectively, with one of said first and second states corresponding to approximately 70% of the time between said successive first signals.

Claim 13

The circuit as claimed in claim 10 in which said circuit path includes a first transistor which conducts when said first means is in said first state to cause the voltage level at said reference point to fall, and said second circuit path includes a second transistor which conducts when said first means is in said second state to cause the voltage level at said reference point to rise.

Claim 14

The circuit as claimed in claim 11 in which said first means includes a timer and said means operatively coupling said reference point with said second input includes an operational amplifier.

Claim 15

The circuit as claimed in claim 12 further comprising means for enabling said blanking pulse to blank said non-data flux reversals after a predetermined pattern in said data stream is received at said input means.

Claim 16

An adaptive synchronizing circuit for synchronizing to a periodic data stream comprising: a first means having first and second inputs and an output for producing a first state at said outputs in response to a first signal from said data stream at said first input; a second means for producing a second state at said output in response to a predetermined condition at said second input; circuit means operatively coupling said output with said second input whereby each of said first and second states is maintained at a relatively stable percentage of the time between successive first signals from said data stream to said first input when the frequency of said first signals varies, with one of said first and second states of said first means providing a utilization pulse corresponding in time to one of said first and second states; said second means including means for producing an increasing voltage starting with a said first signal; and said circuit means having a voltage reference point therein and a circuit path for producing a falling voltage level at said reference point in response to said first state; and means operatively coupling said reference point with said second input whereby said first means is shifted to said second state when the falling voltage level at said second input equals the rising voltage produced by said second means.

Claim 17

An adaptive synchronizing circuit for synchronizing to a periodic data stream comprising: a first means having first and second inputs and an output for producing a first state at said outputs in response to a first signal from said data stream at said first input; a second means for producing a second state at said output in response to a predetermined condition at said second input; circuit means operatively coupling said output with said second input whereby each of said first and second states is maintained at a relatively stable percentage of the time between successive first signals from said data stream to said first input when the frequency of said first signals varies, with one of said first and second states of said first means providing a utilization pulse corresponding in time to one of said first and second states; said second means including means for producing an increasing voltage starting with a said first signal; and said circuit means having a voltage reference point therein and a circuit path for producing a falling voltage level at said reference point in response to said first state; and means operatively coupling said reference point with said second input whereby said first means is shifted to said second state when the falling voltage level at said second input equals the rising voltage produced by said second means.