US3828167A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Detector for self-clocking data with variable digit periods
Assignee: Singer Co
•
Filing: 1972-10-10
•
Granted: 1974-08-06
•
Expires: 1992-10-10
Abstract
Abstract A data detector for eliminating spurious pulses from a train of self-clocking data signals capable of operation over an extremely wide range of digit intervals. Deletion period circuitry including a pair of reversible counters operated simultaneously in opposite directions for establishing successive deletion periods as a function of the actual length of the most recent digit interval.
Inventors
- 👤 W Goldfarb
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 20:17
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B20/14; G11B20/1403; G11B20/1407; G11B20/1419
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
223 words
In a phase modulation read-out system wherein successive recorded information signals are separated in time by a digit period and are translated into a series of pulse signals representing the binary values ''''0'''' and ''''1'''', successive ones of said pulse signals occurring in digit intervals Ti at least some of which vary in duration, a system for eliminating spurious signals occurring within said digit intervals Ti comprising: means for generating a deletion period Di signal which is a fixed fractional portion a of the proceeding one Ti 1 of said digit intervals, said deletion period signal providing a control signal for deleting said spurious signals; and wherein said deletion period signal generating means includes: a pair of reversible counters, control means for enabling a first one of said counters to be counted up at a rate af to measure a digit interval Ti and the remaining one of said counters to be counted down at a rate f to measure a deletion period Di, wherein af is less than f and Di equals a Ti 1; and wherein said deletion period signal generating means provides means for measuring said digit iNterval Ti 1 and means for generating said deletion period signal Di for a period of time given by a Ti 1, where a is a constant less than or equal to one.
Claim 2
Dependent Claim
223 words
In a phase modulation read-out system wherein successive recorded information signals are separated in time by a digit period and are translated into a series of pulse signals representing the binary values ''''0'''' and ''''1'''', successive ones of said pulse signals occurring in digit intervals Ti at least some of which vary in duration, a system for eliminating spurious signals occurring within said digit intervals Ti comprising: means for generating a deletion period Di signal which is a fixed fractional portion a of the proceeding one Ti 1 of said digit intervals, said deletion period signal providing a control signal for deleting said spurious signals; and wherein said deletion period signal generating means includes: a pair of reversible counters, control means for enabling a first one of said counters to be counted up at a rate af to measure a digit interval Ti and the remaining one of said counters to be counted down at a rate f to measure a deletion period Di, wherein af is less than f and Di equals a Ti 1; and wherein said deletion period signal generating means provides means for measuring said digit iNterval Ti 1 and means for generating said deletion period signal Di for a period of time given by a Ti 1, where a is a constant less than or equal to one.
Claim 3
Dependent Claim
23 words
The apparatus of claim 1 wherein the value of a is in the range 0.5 < or = a < or = 1.
Claim 4
Dependent Claim
12 words
The apparatus of claim 1 wherein the value of a is 0.75.
Claim 5
Dependent Claim
171 words
In a phase modulation read-out system wherein successive recorded information signals are separated in time by a digit period and are translated into a series of pulse signals representing the binary values ''''0'''' and ''''1'''', successive ones of said pulse signals occurring in digit intervals Ti at least some of which vary in duration, a system for eliminating spurious signals occurring within said digit intervals Ti comprising means for generating a deletion period Di signal which is a fixed fractional portion a of the preceding one Ti 1 of said digit intervals, said deletion period signal providing a control signal for deleting said spurious signals, wherein said deletion period signal generating means comprises: a pair of reversible counters, control means for enabling a first one of said counters to be counted up at a rate af to measure a digit interval Ti and the remaining one of said counters to be counted down at a rate f to measure a deletion period Di, wherein af f and Di a Ti 1.
Claim 6
Dependent Claim
171 words
In a phase modulation read-out system wherein successive recorded information signals are separated in time by a digit period and are translated into a series of pulse signals representing the binary values ''''0'''' and ''''1'''', successive ones of said pulse signals occurring in digit intervals Ti at least some of which vary in duration, a system for eliminating spurious signals occurring within said digit intervals Ti comprising means for generating a deletion period Di signal which is a fixed fractional portion a of the preceding one Ti 1 of said digit intervals, said deletion period signal providing a control signal for deleting said spurious signals, wherein said deletion period signal generating means comprises: a pair of reversible counters, control means for enabling a first one of said counters to be counted up at a rate af to measure a digit interval Ti and the remaining one of said counters to be counted down at a rate f to measure a deletion period Di, wherein af f and Di a Ti 1.
Claim 7
Dependent Claim
26 words
The apparatus of claim 4 wherein said control means includes means for reversing the roles of said counters at the end of said digit interval Ti.
Claim 8
Dependent Claim
29 words
The apparatus of claim 4 wherein said control means includes means for preventing further decrementing of said remaining one of said counters after a predetermined count has been attained.
Claim 9
Dependent Claim
33 words
The apparatus of claim 4 wherein said control means includes means for preventing the decrementing of said remaining one of said counters during the initial cycle of said deletion period signal generating means.
Claim 10
Dependent Claim
20 words
The apparatus of claim 1 wherein said spurious signals occur whenever two successive information signals have the same binary value.
Claim 11
Dependent Claim
29 words
The apparatus of claim 1 wherein said deletion period signal generator further includes means for generating a synchronizing signal for identifying the beginning of each said digit interval Ti.
Claim 12
Dependent Claim
217 words
A detector for validating information signals in a signal train comprising: means for generating a series of pulse signals representing said information signals in binary form and spurious signals occurring in the digit intervals Ti between successive ones of said information signals; means for generating a deletion period signal serving to identify a deletion period Di during which no valid information signals can occur, said deletion period signal generating means including means for establishing the length of said deletion period Di as a function of the immediately preceding digit interval Ti 1 in accordance with the relation D1 a Ti 1, where a is a constant < or = 1, and wherein said means for establishing the length of said deletion period Di includes a pair of reversible counters, control means for enabling a first one of said counters to be counted up at a rate af to measure said digit intervals Ti and the remaining one of said counters to be counted down at a rate f to measure said deletion periods Di, wherein af < f, said control means including means for reversing the roles of said counters at the end of each of said digit intervals Ti so that each one of said counters counts in opposite directions during successive cycles of detector operation.
Claim 13
Dependent Claim
217 words
A detector for validating information signals in a signal train comprising: means for generating a series of pulse signals representing said information signals in binary form and spurious signals occurring in the digit intervals Ti between successive ones of said information signals; means for generating a deletion period signal serving to identify a deletion period Di during which no valid information signals can occur, said deletion period signal generating means including means for establishing the length of said deletion period Di as a function of the immediately preceding digit interval Ti 1 in accordance with the relation D1 a Ti 1, where a is a constant < or = 1, and wherein said means for establishing the length of said deletion period Di includes a pair of reversible counters, control means for enabling a first one of said counters to be counted up at a rate af to measure said digit intervals Ti and the remaining one of said counters to be counted down at a rate f to measure said deletion periods Di, wherein af < f, said control means including means for reversing the roles of said counters at the end of each of said digit intervals Ti so that each one of said counters counts in opposite directions during successive cycles of detector operation.
Claim 14
Dependent Claim
30 words
The apparatus of claim 10 wherein said control means further includes means for preventing further decrementing of said remaining one of said cOunters after a predetermined count has been attained.
Claim 15
Dependent Claim
31 words
The apparatus of claim 10 wherein said control means further includes means for preventing the decrementing of said remaining one of said counters during the initial cycle of said detector operation.
Claim 16
Dependent Claim
23 words
The apparatus of claim 10 further including means for generating a synchronizing signal for identifying the beginning of each said digit interval Ti.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-08-05 | 1978-02-04 | 1978-08-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-08-05 | 1982-02-04 | 1982-08-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-08-05 | 1986-02-04 | 1986-08-06 | $7700.00 | Window Closed / Lapsed |