Hourmeter-tachometer

Claim 2

An electronic, digital hourmeter-tachometer for use with internal combustion engines or the like comprising: (a) a programmable timer comprising fixed frequency oscillator and divider circuits for outputting system timing pulses when a d.c. power is applied thereto; (b) a pulse pick-up circuit comprising means for receiving a pulse, the frequency of which is indicative of the rpm of the engine and for outputting a pulsed signal having a frequency related to said received signal and means for filtering the pick-up pulses to provide a d.c. output for powering the remainder of the digital hourmeter-tachometer; (c) an electronic hour counter comprising digital counters for counting system timing pulses; (d) a speed counter for counting the pulsed signal output of the pick-up circuit during an update period controlled by the system timing pulses; (e) common display means for sequentially displaying the output of the stored count in the hour counter and the speed counter in response to system timing pulses; (f) means for connecting the d.c. output of the pulse pick-up circuit to power the said programmable timer, hour counter, speed counter, and common display when the pick-up pulses are applied to the pick-up circuit; and (g) battery means for applying a d.c. current to the hour counter when pick-up pulses are not supplied to the pulse pick-up circuit thereby holding the hour count.

Claim 3

A digital hourmeter-tachometer according to claim 1 further comprising a shut-down circuit comprising: a counter for counting the pulsed signal output of the pick-up circuit for a time period controlled by the system timing pulses and outputting a shut-down signal to the engine if the count exceeds a preselected limit.

Claim 4

The digital hour-tachometer according to claim 1 further comprising means for differrentiating between the two display counts by blanking one or more digits of the display while the speed count is displayed.

Claim 5

The digital hourmeter-tachometer according to claim 3 further comprising an IC flip-flop means for insuring display of the speed count commences simultaneously with the completion of a said update period.

Claim 6

The digital hourmeter-tachometer according to claim 1 further comprising an IC flip-flop means and wherein the battery only powers the hour counter and said IC flip-flop means, and the hour counter and IC flip-flop means are the only active circuits when pick-up pulses are not supplied to the pick-up pulse circuit and said IC flip-flop means being provided to output a signal placing all buffered outputs of the hour counter in a high impedance state such that no live digital signal can be applied to any portion of the circuit not powered by the battery.

Claim 7

The digital hourmeter-tachometer according to claim 5 further comprising a time delay circuit means connected to an inverter output, the input of which is connected to the pulsed signal output of the pick-up pulse circuit, for switching the said IC flip-flop means to output said signal shortly after cessation of the pulsed signal output.

Claim 8

A digital hourmeter-tachometer for use with internal combustion engines or the like comprising: (a) a programmable timer comprising fixed frequency oscillator and divider circuits for outputting system timing pulses when a d.c. power is applied thereto; (b) a pulse pick-up circuit comprising means for receiving a pulse, the frequency of which is indicative of the rpm of the engine and for outputting a pulsed signal having a frequency related to said received signal and means for filtering the pick-up pulses to provide a d.c. output for powering the remainder of the digital hourmeter-tachometer; (c) an hour counter comprising a plurality of cascaded BCD digital counters for counting system timing pulses and a plurality of buffers; (d) a speed counter comprising a plurality of cascaded BCD digital counters for counting the pulsed signal output of the pick-up circuit during an update period controlled by the system timing pulses and a plurality of buffers; (e) common display means comprising a plurality of BCD to seven segment drivers and a corresponding plurality of seven segment LCD displays for sequentially displaying the output of the stored count in the hour counter and the speed counter in response to system timing pulses; (f) a BCD bus connected to each BCD digital counter of the hour counter and each BCD digital counter of the speed counter through said plurality of buffers and said BCD bus also connected to each seven segment driver of the common display means; (g) an address bus connected to the said plurality of buffers and latch enable terminals of each seven segment driver of the common display means; (h) multiplexing means connected to said address bus for controlling the transfer of the count in each BCD digital counter to the display means; (i) a flip-flop means responsive to signals from the programmable timer, said flip-flop for outputting signals to permit either the hour counter or the speed counter access to the address and data buses, (j) means for connecting the d.c. output of the pulse pick-up circuit to power the said timer, hour counter, speed counter and common display circuits when the pick-up pulses are applied to the pick-up circuit; and (k) battery means for applying a d.c. output to the hourmeter when pick-up pulses are not supplied to the pulse pick-up circuit thereby holding the hour count.

Claim 9

A digital hourmeter-tachometer for use with internal combustion engines or the like comprising: (a) a programmable timer comprising fixed frequency oscillator and divider circuits for outputting system timing pulses when a d.c. power is applied thereto; (b) a pulse pick-up circuit comprising means for receiving a pulse, the frequency of which is indicative of the rpm of the engine and for outputting a pulsed signal having a frequency related to said received signal and means for filtering the pick-up pulses to provide a d.c. output for powering the remainder of the digital hourmeter-tachometer; (c) an hour counter comprising a plurality of cascaded BCD digital counters for counting system timing pulses and a plurality of buffers; (d) a speed counter comprising a plurality of cascaded BCD digital counters for counting the pulsed signal output of the pick-up circuit during an update period controlled by the system timing pulses and a plurality of buffers; (e) common display means comprising a plurality of BCD to seven segment drivers and a corresponding plurality of seven segment LCD displays for sequentially displaying the output of the stored count in the hour counter and the speed counter in response to system timing pulses; (f) a BCD bus connected to each BCD digital counter of the hour counter and each BCD digital counter of the speed counter through said plurality of buffers and said BCD bus also connected to each seven segment driver of the common display means; (g) an address bus connected to the said plurality of buffers and latch enable terminals of each seven segment driver of the common display means; (h) multiplexing means connected to said address bus for controlling the transfer of the count in each BCD digital counter to the display means; (i) a flip-flop means responsive to signals from the programmable timer, said flip-flop for outputting signals to permit either the hour counter or the speed counter access to the address and data buses, (j) means for connecting the d.c. output of the pulse pick-up circuit to power the said timer, hour counter, speed counter and common display circuits when the pick-up pulses are applied to the pick-up circuit; and (k) battery means for applying a d.c. output to the hourmeter when pick-up pulses are not supplied to the pulse pick-up circuit thereby holding the hour count.