Selectively operable mask generator

Claim 2

A mask generator for generating a mask having a plurality of bits at the mask generator output and having a selective number of inhibiting bits of a predetermined value in said plurality of output bits, comprising: decoder means for receiving a first set of address signals representing the beginning inhibiting bit of the mask and for receiving a second set of address signals representing the address of the end inhibiting bit of the mask, and for converting said first and second set of address signals to a generate signal corresponding to each of said output bits, including an enabled generate signal, and to a propagate signal corresponding to each of said output bits, including an enabled propagate signal; and look-ahead carry circuit means for receiving said generate and propagate signals and for producing said output bits, said outputs bits including said inhibiting bits beginning with an inhibiting bit corresponding to said enabled generate signal and continuing up to an inhibiting bit corresponding to said enabled propagate signal, said look-ahead carry circuit means including: first gate means associated with each one of said output bits for receiving the generate signal corresponding to each of any output bits preceding its associated one of said output bits and for receiving the propagate signal corresponding to each of any output bits preceding its associated one of said output bits and the propagate signal corresponding to its associated one of said output bits; and second gate means associated with each one of said output bits for receiving the output of the first gate means associated with its associated one of said output bits and the generate signal corresponding to its associated one of said output bits.

Claim 3

The mask generator of claim 1 wherein said first gate means includes a number of logic gates increasing in magnitude in relation to the number of preceding output bits.

Claim 4

The mask generator of claim 1 wherein the last output bit in said plurality of output bits is connected to the first gate means associated with each of the other output bits in said plurality of output bits.

Claim 5

A mask generator for generating a mask having a plurality of bits at the mask generator output and having a selective number of inhibiting bits of a predetermined value in said plurality of output bits, comprising: decoder means for receiving a first set of address signals representing the beginning inhibiting bit of the mask and for receiving a second set of address signals representing the address of the end inhibiting bit of the mask, and for converting said first and second set of address signals to a generate signal corresponding to each of said outputs, including an enabled generate signal, and to a propagate signal corresponding to each of said output bits, including an enabled propagate signal; and look-ahead carry circuit means for receiving said generate and propagate signals, and for producing said output bits, said output bits including said inhibiting bits beginning with an inhibiting bit corresponding to said enabled generate signal and continuing up to an inhibiting bit corresponding to said enabled propagate signal, said look-ahead carry circuit means including: a plurality of first level look-ahead carry circuits for generating said plurality of output bits; and a second level look-ahead carry circuit associated with each of said first level circuits for providing a second level output signal to the next following first level circuit, said second level output signal indicating if an inhibiting bit has either been both generated in and propagated through its associated first level circuit, or has been propagated through its associated first level circuit.

Claim 6

A mask generator for generating a mask having a plurality of bits at the mask generator output and having a selective number of inhibiting bits of a predetermined value in said plurality of output bits, comprising: decoder means for receiving a first set of address signals representing the beginning inhibiting bit of the mask and for receiving a second set of address signals representing the address of the end inhibiting bit of the mask, and for converting said first and second set of address signals to a generate signal corresponding to each of said outputs, including an enabled generate signal, and to a propagate signal corresponding to each of said output bits, including an enabled propagate signal; and look-ahead carry circuit means for receiving said generate and propagate signals, and for producing said output bits, said output bits including said inhibiting bits beginning with an inhibiting bit corresponding to said enabled generate signal and continuing up to an inhibiting bit corresponding to said enabled propagate signal, said look-ahead carry circuit means including: a plurality of first level look-ahead carry circuits for generating said plurality of output bits; and a second level look-ahead carry circuit associated with each of said first level circuits for providing a second level output signal to the next following first level circuit, said second level output signal indicating if an inhibiting bit has either been both generated in and propagated through its associated first level circuit, or has been propagated through its associated first level circuit.

Claim 7

The mask generator of claim 4, wherein each one of said first level look-ahead carry circuits generates a group generate signal indicating if that one of said first level circuits has received said enabled generate signal and not said enabled propagate signal and a group propagate signal indicating if that one of said first level circuits has not received said enabled propagate signal, and wherein the output of each first level circuit is connected to the input of each second level circuit so that the group generate signal of each first level circuit is received by the second level circuit associated with every other first level circuit, and so that the group propagate signal of each first level circuit is received by every second level circuit.

Claim 8

In a computer processor, a mask generator for generating a plurality of output bits, with a preselected group of consecutive inhibiting bits in said output bits, comprising: a first decoder circuit for receiving a first address signal representing a beginning inhibiting bit and producing a plurality of generate signals in response to said first address signal, one generate signal corresponding to each of said output bits, with the generate signal corresponding to said beginning inhibiting bit being in an enabled condition and the other generate signals being in a non-enabled condition; a second decoder circuit for receiving a second address signal representing the end inhibiting bit and producing a plurality of propagate signals in response to said second address signal, one propagate signal corresponding to each of said output bits, with the propagate signal following the propagate signal corresponding to said end inhibiting bit being in an enabled condition and the other propagate signals being in a non-enabled condition; and look-ahead carry circuit means for receiving said generate and propagate signals and fixing said inhibiting bits at a predetermined logic level, said look-ahead carry circuit means including first and second logic gate means associated with each output bit; said first gate means for each associated output bit receiving the generate signals corresponding to any preceding output bits and the propagate signals corresponding to any preceding output bits and the propagate signal corresponding to the output bit associated with said first gate means, and said first gate means associated with each output bit except the last output bit also receiving the signal at the last output bit; and said second gate means for each associated output bit receiving the output of said first gate means and the generate signal corresponding to the output bit associated with said second gate means.

Claim 9

In a computer processor, a mask generator for generating a plurality of output bits, with a preselected group of consecutive inhibiting bits in said output bits, comprising: a first decoder circuit for receiving a first address signal representing a beginning inhibiting bit and producing a plurality of generate signals in response to said first address signal, one generate signal corresponding to each of said output bits, with the generate signal corresponding to said beginning inhibiting bit being in an enabled condition and the other generate signals being in a non-enabled condition; a second decoder circuit for receiving a second address signal representing the end inhibiting bit and producing a plurality of propagate signals in response to said second address signal, one propagate signal corresponding to each of said output bits, with the propagate signal following the propagate signal corresponding to said end inhibiting bit being in an enabled condition and the other propagate signals being in a non-enabled condition; and look-ahead carry circuit means for receiving said generate and propagate signals and fixing said inhibiting bits at a predetermined logic level, said look-ahead carry circuit means including first and second logic gate means associated with each output bit; said first gate means for each associated output bit receiving the generate signals corresponding to any preceding output bits and the propagate signals corresponding to any preceding output bits and the propagate signal corresponding to the output bit associated with said first gate means, and said first gate means associated with each output bit except the last output bit also receiving the signal at the last output bit; and said second gate means for each associated output bit receiving the output of said first gate means and the generate signal corresponding to the output bit associated with said second gate means.