US4180749A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Input buffer for integrated injection logic circuits
Assignee: Texas Instruments Inc
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Filing: 1977-07-18
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Granted: 1979-12-25
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Expires: 1997-07-18
Abstract
Abstract An input buffer gate for integrated injection logic (I 2 L) circuits, including a multiple-collector transistor wherein a first collector is electrically common with the base thereof, a second (Schottky) collector is connected to receive an input signal, and a third collector which drives internal I 2 L gates. The buffer has a high input breakdown voltage, virtually no input capacitance, power-up/power-down capability at logic "1" and virtually no input current at logic "0", very low storage time, and an input "1" threshold of about 0.5 volts.
Inventors
- 👤 Benjamin J. Sloan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 09:25
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/018; H03K19/01806; H03K19/01818; H10; H10D; H10D84/00; H10D84/60; H10D84/65
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
74 words
A circuit for achieving compatibility between first and second systems operating at different voltage levels, comprising an inverted multiple-collector transistor wherein a first collector thereof is electrically common with the base thereof, a second collector including a Schottky barrier is connected to receive a relatively high-voltage signal from said first system, and a third collector is connected as the input to a second system and provides a lower-voltage signal compatible with said second system.
Claim 2
Dependent Claim
74 words
A circuit for achieving compatibility between first and second systems operating at different voltage levels, comprising an inverted multiple-collector transistor wherein a first collector thereof is electrically common with the base thereof, a second collector including a Schottky barrier is connected to receive a relatively high-voltage signal from said first system, and a third collector is connected as the input to a second system and provides a lower-voltage signal compatible with said second system.
Claim 3
Dependent Claim
19 words
A circuit as in claim 1 further including forward-biased rectifying means in the input line to said second collector.
Claim 4
Dependent Claim
14 words
A circuit as in claim 1 wherein said second collector is a metal-semiconductor barrier.
Claim 5
Dependent Claim
22 words
A circuit as in claim 1 wherein the area of the second collector is about three times that of the third collector.
Claim 6
Dependent Claim
103 words
An integrated circuit comprising an inverted, multiple-collector transistor and a complementary lateral transistor, the emitter of the former being electrically common with the base of the latter, and the collector of the latter being common with the base of the former, said multiple collectors including a first collector coupled to the base of the inverted transistor, a second collector comprising a Schottky barrier, coupled to receive a relatively high voltage input signal, and a third collector coupled to an integrated injection logic system as an input thereto, whereby the degree of saturation of the Schottky collector controls the gain of the other collectors.
Claim 7
Dependent Claim
103 words
An integrated circuit comprising an inverted, multiple-collector transistor and a complementary lateral transistor, the emitter of the former being electrically common with the base of the latter, and the collector of the latter being common with the base of the former, said multiple collectors including a first collector coupled to the base of the inverted transistor, a second collector comprising a Schottky barrier, coupled to receive a relatively high voltage input signal, and a third collector coupled to an integrated injection logic system as an input thereto, whereby the degree of saturation of the Schottky collector controls the gain of the other collectors.
Claim 8
Dependent Claim
35 words
A circuit as in claim 5 wherein the ratio of areas of said first, second and third collectors is such that the base drive to the third collector approaches zero when the second collector saturates.
Claim 9
Dependent Claim
15 words
A circuit as in claim 6 wherein the ratio of said areas is 1:10:10, respectively.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-12-24 | 1983-06-25 | 1983-12-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-12-24 | 1987-06-25 | 1987-12-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-12-24 | 1991-06-25 | 1991-12-25 | $7700.00 | Window Closed / Lapsed |