US4176781A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Apparatus for monitoring and checking processor operation sequences
Assignee: International Business Machines Corp
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Filing: 1978-04-03
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Granted: 1979-12-04
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Expires: 1998-04-03
Abstract
Abstract Apparatus for monitoring and controlling the sequence analysis of processor operations in electronic digital computers. Each flip-flop in a flip-flop chain is associated with an operational step for setting up a monitoring and check sequence. The sequence is controlled by a flip-flop ring and consists of several steps each of which represents a monitoring or check function. An oscillator signal is fed to all flip-flop stages, together with a further control signal. Switching of flip-flops is effected in such a manner that at any one time only one flip-flop is on, its output signal and a coinciding oscillator signal generating a control signal which is converted in an address generator into an address for fetching a subroutine from a storage to control the monitoring and check function associated with the flip-flop.
Inventors
- 👤 Juergen Huesing
- 👤 Hans H. Lampe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 23:51
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/36; G06F11/362; G06F11/3648; G06F11/30; G06F11/3003; G06F11/3024; G06F11/3089
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
180 words
Apparatus for monitoring and controlling sequence analysis of processor operations in an electronic digital computer, comprising: a flip-flop chain in which each flip-flop is associated with an operational step for setting up a monitoring and check sequence; a flip-flop ring, comprising a group of flip-flops within said chain for controlling the monitoring and check sequence; means for conducting an oscillator signal to a reset input of all of said flip-flops; said flip-flop chain including logic means for conducting control signals to a set input of all of said flip-flops; each of said flip-flops being so designed that a concurrence of signals of the set and reset inputs will cause the flip-flop to change state; said logic means permitting only one flip-flop to be set at any time; storage means; address generating means; and means connected between said flip-flops and said address generating means, responsive to the concurrence of an oscillator signal and a set state of one flip-flop to cause said address generating means to generate the address in said storage means of a subroutine associated with said one flip-flop.
Claim 2
Dependent Claim
180 words
Apparatus for monitoring and controlling sequence analysis of processor operations in an electronic digital computer, comprising: a flip-flop chain in which each flip-flop is associated with an operational step for setting up a monitoring and check sequence; a flip-flop ring, comprising a group of flip-flops within said chain for controlling the monitoring and check sequence; means for conducting an oscillator signal to a reset input of all of said flip-flops; said flip-flop chain including logic means for conducting control signals to a set input of all of said flip-flops; each of said flip-flops being so designed that a concurrence of signals of the set and reset inputs will cause the flip-flop to change state; said logic means permitting only one flip-flop to be set at any time; storage means; address generating means; and means connected between said flip-flops and said address generating means, responsive to the concurrence of an oscillator signal and a set state of one flip-flop to cause said address generating means to generate the address in said storage means of a subroutine associated with said one flip-flop.
Claim 3
Dependent Claim
32 words
The apparatus of claim 1 further including: means for causing said logic means to vary the sequence in which said flip-flops are set in dependence upon conditions of said electronic digital computer.
Claim 4
Dependent Claim
30 words
The apparatus of claim 1 wherein: the set output of each of said flip-flops forms a control signal conducted by said logic means to the set input of another flip-flop.
Claim 5
Dependent Claim
24 words
The apparatus of claim 3 wherein: each of said flip-flops is responsive to the trailing edges of signals at its inputs to change state.
Claim 6
Dependent Claim
32 words
The apparatus of claim 3 further including: means for causing said logic means to vary the sequence in which said flip-flops are set in dependence upon conditions of said electronic digital computer.
Claim 7
Independent Claim
41 words
The apparatus of claims 1, 2, 3 or 5 further including: a keyboard; and means responsive to activation of a first predetermined key on said keyboard to set a first flip-flop in said chain to initiate said monitoring and check sequence.
Claim 8
Dependent Claim
26 words
The apparatus of claim 6 further including: means to cause cyclic setting of the flip-flops in said flip-flop ring, thereby repeating said monitoring and check sequence.
Claim 9
Dependent Claim
26 words
The apparatus of claim 7 further including: means responsive to activation of a second predetermined key on said keyboard to cause cessation of said cyclic repetition.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-12-03 | 1983-06-04 | 1983-12-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-12-03 | 1987-06-04 | 1987-12-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-12-03 | 1991-06-04 | 1991-12-04 | $7700.00 | Window Closed / Lapsed |