Method for producing a semiconductor fixed value ROM

Claim 2

In a method for producing a fixed value memory in the form of a programmable, monolithically integrated circuit, wherein the fixed information is introduced into a semiconductor memory as a binary coded bit pattern in process stages integrated into or following the conventional production sequence for semiconductor circuits including the direct transfer of occupation of the memory cells as prepared by software, with the elimination of masks comprising the steps of: providing a semiconductor memory which was produced according to the MOS technique and including MOS transistor memory cells arranged to form a matrix and conductor paths substantially connecting the gate terminals of said transistors in rows arranged on the surface of said memory; producing a masking layer corresponding to the desired coded bit pattern on said surface of said memory by applying a layer of radiation sensitive lacquer (electron resist) to said surface of said memory and deflecting a focused electron beam according to a given bit pattern under the control of a computer to illuminate said lacquer layer at selected points to render the lacquer at the illuminated points soluble; and thereafter selectively processing said memory to cause the memory cells of the memory circuit below the masking layer to receive the stored value by removing the portions of the conductor paths disposed below the soluble portions of the lacquer in an etching process; the improvement wherein the potential of the gate terminals of the memory transistors is used as the information carrier and wherein said illuminated points are such as to cause selected gate terminals to be disconnected from the associated conductor during said etching process.

Claim 3

A method as defined in claim 1, further comprising: in an additional etching process, completely removing the gate oxide layers of the MOS transistors which were exposed in the mask openings; and covering at least the exposed regions of the surface of the semiconductor memory with a passivation layer.

Claim 4

A method as defined in claim 1 wherein said step of selectively processing further includes: additionally removing the metallization from the gate terminals of the transistors which are disconnected from the associated conductors according to the desired occupation; and thereafter implanting ions in these gate regions so as to set a stable switching state for the associated MOS transistor memory cell disposed therebelow.

Claim 5

A method as defined in claim 1 wherein: all of the memory transistors are represented in one memory matrix; the manufacturing process of the semiconductor memory takes place using conventional techniques to the point where the structure of the metallization layer for the conductors has been applied; the circuits are then tested and stored if desired; and are personalized according to the process of the invention to store the desired information as subsequently desired.

Claim 6

In a method for producing a fixed value memory in the form of a programmable, monolithically integrated circuit wherein the fixed information is introduced into a semiconductor memory as binary coded bit pattern in process stages integrated into or following the conventional production sequence for semiconductor circuits including the direct transfer of occupation of the memory cells as prepared by software, with the elimination of masks comprising the steps of producing a masking layer on the surface of the semiconductor memory corresponding to the desired coded bit pattern by the deflection of an electron or ion beam under the control of a computer, and thereafter selectively processing the memory to cause the memory cells of the memory circuit below the masking layer to receive the stored value; the improvement wherein: said semiconductor memory comprises a matrix of MOS transistor memory cells; the gate terminals of the MOS transistors are substantially connected together in rows by conductor paths on the surface of said semiconductor memory; said step of producing a masking layer includes applying a radiation sensitive lacquer layer to the surface of said semiconductor memory, illuminating selected portions of said lacquer layer by means of an electron beam according to a given pattern so that, after a subsequent etching process in which the illuminated portions of said lacquer layer as well as the portions of the metal layers disposed therebelow are removed, the gate terminals of all MOS transistors which are to store one of the two binary states of the desired bit pattern are separated from the conductor path connecting the MOS transistors in the associated rows; and said step of selectively processing comprises subjecting said memory to an etching process to remove the illuminated portions of the lacquer layer and the underlying metal layer portions.

Claim 7

In a method for producing a fixed value memory in the form of a programmable, monolithically integrated circuit wherein the fixed information is introduced into a semiconductor memory as binary coded bit pattern in process stages integrated into or following the conventional production sequence for semiconductor circuits including the direct transfer of occupation of the memory cells as prepared by software, with the elimination of masks comprising the steps of producing a masking layer on the surface of the semiconductor memory corresponding to the desired coded bit pattern by the deflection of an electron or ion beam under the control of a computer, and thereafter selectively processing the memory to cause the memory cells of the memory circuit below the masking layer to receive the stored value; the improvement wherein: said semiconductor memory comprises a matrix of MOS transistor memory cells; the gate terminals of the MOS transistors are substantially connected together in rows by conductor paths on the surface of said semiconductor memory; said step of producing a masking layer includes applying a radiation sensitive lacquer layer to the surface of said semiconductor memory, illuminating selected portions of said lacquer layer by means of an electron beam according to a given pattern so that, after a subsequent etching process in which the illuminated portions of said lacquer layer as well as the portions of the metal layers disposed therebelow are removed, the gate terminals of all MOS transistors which are to store one of the two binary states of the desired bit pattern are separated from the conductor path connecting the MOS transistors in the associated rows; and said step of selectively processing comprises subjecting said memory to an etching process to remove the illuminated portions of the lacquer layer and the underlying metal layer portions.

Claim 8

A method as defined in claim 5 wherein said given pattern is such that the gate terminals of the MOS transistors which were separated from the row conductor according to the desired bit pattern are connected to a further conductor path which is at ground potential.

Claim 9

A method as defined in claim 5 wherein: all of the memory transistors are represented in one memory matrix; the manufacturing process of the semiconductor memory takes place using conventional techniques to the point where the structure of the metallization layer for the conductors has been applied; the circuits are then tested and stored if desired; and are personalized according to the process of the invention to store the desired information as subsequently desired.