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US4171765A
Expired / Lapsed
US
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Error detection system
Assignee: EMC Corp
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Filing: 1978-06-21
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Granted: 1979-10-23
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Expires: 1998-06-21
Abstract
Abstract Error detection circuitry for use in a data processing system which utilizes a programmable logic array for controlling, during a write operating mode, the generation of a write error word by an error register, which write error word is thereupon stored together with the associated data words in a data storage device and for controlling, during a read operating mode, the generation of a read error word, the error register thereupon effectively comparing the read error word with the originally stored write error word to produce a remainder word when an error is present.
Inventors
- 👤 Louis A. Lemone
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 15:28
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B20/18; G11B20/1833
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
253 words
Error detection circuitry for use in a data processing system having a data storage device comprising first register means capable of accepting data words in parallel form and supplying said parallel data words in serial form and further capable of accepting data words in serial form and supplying said serial data words in parallel form; error register means capable of accepting serial data words and producing an error word in response thereto; programable logic array means programmed to perform the following operations: (1) controlling, during a write operating mode, the supplying of serial data words from said first register means to said data storage device and to said error register means, said error register means thereby producing a write error word, (2) controlling, during said write operating mode, the supplying of said write error word from said error register means to said data storage device for storage therein with said data words, (3) controlling, during a read operating mode, the supplying of data words from said data storage device to said first register means and to said error register means, said error register means thereby producing a read error word in response thereto, (4) controlling, during said read operating mode, the supplying of said write error word from said data storage device to said error register means when said read error word has been produced therein, said error register means thereby providing a remainder word, (5) controlling, during said read operating mode, the supplying of said remainder word to said first register means.
Claim 2
Dependent Claim
253 words
Error detection circuitry for use in a data processing system having a data storage device comprising first register means capable of accepting data words in parallel form and supplying said parallel data words in serial form and further capable of accepting data words in serial form and supplying said serial data words in parallel form; error register means capable of accepting serial data words and producing an error word in response thereto; programable logic array means programmed to perform the following operations: (1) controlling, during a write operating mode, the supplying of serial data words from said first register means to said data storage device and to said error register means, said error register means thereby producing a write error word, (2) controlling, during said write operating mode, the supplying of said write error word from said error register means to said data storage device for storage therein with said data words, (3) controlling, during a read operating mode, the supplying of data words from said data storage device to said first register means and to said error register means, said error register means thereby producing a read error word in response thereto, (4) controlling, during said read operating mode, the supplying of said write error word from said data storage device to said error register means when said read error word has been produced therein, said error register means thereby providing a remainder word, (5) controlling, during said read operating mode, the supplying of said remainder word to said first register means.
Claim 3
Dependent Claim
19 words
Error detection circuitry in accordance with claim 1 wherein said data storage device is a magnetic disk storage unit.
Claim 4
Dependent Claim
129 words
Error detection circuitry in accordance with claim 2 wherein said programmable logic array means has a first selected number of inputs which includes a plurality of bits from said error register means; serial data words from said first register means to be supplied to said magnetic disk storage unit; serial data words from said magnetic disk storage unit to be supplied to said first register means; a control signal for controlling the enabling of said error register means, and coded control signals for controlling the generation of said write and read error words during said write and read operating modes, respectively; for controlling the supplying of said write error to said magnetic disk storage unit; and for controlling the supplying of said remainder word to said first regiater means.
Claim 5
Dependent Claim
89 words
Error detection circuitry in accordance with claim 3 wherein said programmable logic array means is programmed so as to provide said write error in accordance with a first selected polynomial function determined by a first selected number of said plurality of bits from said error register and so as to provide said read error word in accordance with a second selected polynomial function determined by second selected ones of said plurality of bits from said error register means, said second polynomial function being equivalent to said first polynomial function.
Claim 6
Dependent Claim
44 words
Error detection circuitry in accordance with claim 4 wherein said first selected polynomial function is the function x 32 +x 23 +x 21 +x 11 +x 2 +1 and said second polynomial function is the function (x 11 +x 2 +1) (x 21 +1).
Claim 7
Dependent Claim
63 words
Error detection circuitry in accordance with claim 5 wherein said error register means is a 32-bit register and said first selected ones of said plurality of bits from said error register means are bits φ, 9, 11, 21 and 3φ and said second selected ones of said plurality of bits from said error register means are bits 8, 1φ, 2φ, 29 and 31.
Claim 8
Dependent Claim
76 words
Error detection circuitry for use in a data processing system comprising means for producing write and read error words in response to data words during write and read operating modes, respectively, and for comparing said write and read error words to produce remainder words therefrom; and programmable logic array means programmed to control the producing of said write and read error words and to control the producing of said remainder words in accordance with said comparison.
Claim 9
Dependent Claim
76 words
Error detection circuitry for use in a data processing system comprising means for producing write and read error words in response to data words during write and read operating modes, respectively, and for comparing said write and read error words to produce remainder words therefrom; and programmable logic array means programmed to control the producing of said write and read error words and to control the producing of said remainder words in accordance with said comparison.
Claim 10
Dependent Claim
33 words
Error detection circuitry in accordance with claim 7 wherein said programmable logic array means is programmed to control the producing of said write and said read error words in accordance with selected polynomials.
Claim 11
Dependent Claim
41 words
Error detection circuitry in accordance with claims 7 or 8 wherein said programmable logic array means is programmed to control the producing of said write and said read error words and the producing of said remainder words in a multiplexed manner.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-10-22 | 1983-04-23 | 1983-10-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-10-22 | 1987-04-23 | 1987-10-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-10-22 | 1991-04-23 | 1991-10-23 | $7700.00 | Window Closed / Lapsed |