Overshoot suppression circuitry for ternary pulses

Claim 3

The system of claim 1, in which the given period of time is smaller than the minimum interval between successive ternary pulses.

Claim 4

The system of claim 1, in which the detecting means comprises a resettable up-down counter having first, second, third, and fourth successive states, a count up input, and a count down input, one of the indicating circuits transmits an indication to the count up input to change the state of the counter in one direction, and the other indicating circuit transmits an indication to the count down input to change the state of the counter in the other direction, and means for resetting the counter into the second or third state and for generating an error signal when the counter assumes the first or fourth state.

Claim 5

The system of claim 3, additionally comprising means for automatically controlling the level of the ternary pulses from the source to counteract variations thereof.

Claim 6

The system of claim 1, in which the first indicating circuit comprises a first switching transistor having an output connected to the load and an input, the output of the first transistor being high when its input is low and vice versa, and first means for connecting the source to the input of the first switching transistor to couple thereto ternary pulses of positive polarity to the exclusion of ternary pulses of negative polarity; the second indicating circuit comprises a second switching transistor having an output connected to the load and an input, the output of the second transistor being high when its input is low and vice versa, and second means for connecting the source to the input of the second switching transisitor to couple thereto ternary pulses of negative polarity to the exclusion of ternary pulses of positive polarity; the means for inhibiting transmission by the first indicating circuit comprises a first inverter having a significant transmission delay relative to the duration of the ternary pulses but smaller than the minimum interval between successive ternary pulses, the first inverter having an input connected to the output of the second switching transistor and an output, and a first clamping circuit having an input to which the output of the first inverter is connected, and an output connected to the input of the first switching transistor, the output of the clamping circuit clamping the input of the first switching transistor low when the input of the first clamping circuit is high to prevent the output of the first switching transistor from becoming low; and the means for inhibiting transmission of an indication by the second indicating circuit comprises a second inverter having a significant transmission delay relative to the duration of the ternary pulses but smaller than the minimum interval between successive ternary pulses, the second inverter having an input connected to the output of the first switching transistor and an output, and a second clamping circuit having an input to which the output of the second inverter is connected and an output that clamps the input of the second switching transistor low when the input of the second clamping circuit is high to prevent the output of the second transistor from becoming low.

Claim 7

The system of claim 5, in which the load comprises means for detecting the occurrence of successive ternary pulses of the same polarity.

Claim 8

The system of claim 6, in which the detecting means comprises a resettable up-down counter having first, second, third, and fourth successive states, a count up input, and a count down input, one of the indicating circuits transmits an indication to the count up input to change the state of the counter in one direction, and the other indicating circuit transmits an indication to the count down input to change the state of the counter in the other direction, and means for resetting the counter into the second or third state and for generating an error signal when the counter assumes the first or fourth state.

Claim 9

The system of claim 7, in which the source has first and second ungrounded output terminals, the first connecting means comprising a diode poled in a given direction relative to the first output terminal, and the second connecting means comprising a diode poled in the given direction relative to the second output terminal.

Claim 10

The system of claim 3, additionally comprising a bias source for energizing the indicating circuits, means for effectively disconnecting the bias source from the indicating circuits in the absence of a minimum pulse level at the source, means for sensing the pulse level at the source, and means responsive to the sensing means for connecting the bias source to the indicating circuits when the minimum pulse level at the source is exceeded.

Claim 13

The system of claim 10, in which the first switch comprises a first switching transistor having an input and an output, the first transistor being nonconductive in the absence of pulses of a given polarity at the first output terminal of the source and being conductive in the presence of pulses of the given polarity at the first output terminal of the source; the second switch comprises a second switching transistor having an input and an output, the second transistor being nonconductive in the absence of pulses of the given polarity at the second output terminal of the source and being conductive in the presence of pulses of the given polarity at the second output terminal of the source; the means for opening the second switch comprises a clamping circuit for clamping the input of the second transistor to a potential that maintains the second transistor nonconducting when the clamping circuit is actuated, and a feedback connection with transmission delay from the output of the first switching transistor to the clamping circuit to actuate the clamping circuit when the first transistor is conducting; and the means for opening the first switch comprises a clamping circuit for clamping the input of the first transistor to a potential that maintains the first transistor nonconducting when the clamping circuit is actuated, and a feedback connection with transmission delay from the output of the second transistor to the clamping circuit to actuate the clamping circuit when the second transistor is conducting.

Claim 14

Overshoot suppression circuitry for a source of ternary pulses having first and second ungrounded output terminals, the ternary pulses being subject to baseline overshoot, the system comprising: a load a first switching transistor having an input connected to the first output terminal of the source and an output connected to the load, the output of the first transistor being high when its input is low and vice versa; a second switching transistor having an input connected to the second output terminal of the source and an output connected to the load, the output of the second transistor being high when its input is low and vice versa; a first inverter having a significant transmission delay relative to the duration of the ternary pulses, but smaller than the minimum interval between successive ternary pulses, the first inverter having an input connected to the output of the second transistor and an output; a second inverter having a significant transmission delay relative to the duration of the ternary pulses, but smaller than the minimum interval between successive ternary pulses, the second inverter having an input connected to the output of the first transistor and an output; a first clamping circuit having an input to which the output of the first inverter is connected and an output connected to the input of the first transistor, the output of the first clamping circuit clamping the input of the first transistor low when the input of the first clamping circuit is high, to prevent the output of the first transistor from going low; a second clamping circuit having an input to which the output of the second inverter is connected and an output that clamps the input of the second transistor low when the input of the second clamping circuit is high, to prevent the output of the second transistor from going low; means for applying a low bias level to the first and second switching transistors in the absence of a minimum pulse level at the inputs of the first and second switching transistors; means for sensing the pulse level at the inputs to the first and second switching transistors; and means responsive to the sensing means when the minimum pulse level at the inputs to the switching transistors is exceeded for applying a high bias level to the first and second switching transistors.

Claim 15

Overshoot suppression circuitry for a source of ternary pulses having first and second ungrounded output terminals, the ternary pulses being subject to baseline overshoot, the system comprising: a load a first switching transistor having an input connected to the first output terminal of the source and an output connected to the load, the output of the first transistor being high when its input is low and vice versa; a second switching transistor having an input connected to the second output terminal of the source and an output connected to the load, the output of the second transistor being high when its input is low and vice versa; a first inverter having a significant transmission delay relative to the duration of the ternary pulses, but smaller than the minimum interval between successive ternary pulses, the first inverter having an input connected to the output of the second transistor and an output; a second inverter having a significant transmission delay relative to the duration of the ternary pulses, but smaller than the minimum interval between successive ternary pulses, the second inverter having an input connected to the output of the first transistor and an output; a first clamping circuit having an input to which the output of the first inverter is connected and an output connected to the input of the first transistor, the output of the first clamping circuit clamping the input of the first transistor low when the input of the first clamping circuit is high, to prevent the output of the first transistor from going low; a second clamping circuit having an input to which the output of the second inverter is connected and an output that clamps the input of the second transistor low when the input of the second clamping circuit is high, to prevent the output of the second transistor from going low; means for applying a low bias level to the first and second switching transistors in the absence of a minimum pulse level at the inputs of the first and second switching transistors; means for sensing the pulse level at the inputs to the first and second switching transistors; and means responsive to the sensing means when the minimum pulse level at the inputs to the switching transistors is exceeded for applying a high bias level to the first and second switching transistors.

Claim 16

The circuitry of claim 12, in which the first and second clamping circuits each comprise a transistor having an emitter connected to a reference potential suitable to clamp the input of the corresponding switching transistor low, a base that is the input and a collector that is the output, each clamping transistor being conductive when its input is high to couple the reference potential to the input of the corresponding switching transistor, and being nonconductive when its input is low.

Claim 17

The circuitry of claim 13, in which the first and second switching transistors are conductive when their outputs are low and are nonconductive when their outputs are high, the first and second switching transistors becoming conductive when a ternary pulse is applied to the respective inputs while the corresponding clamping circuit is not actuated.

Claim 18

The circuitry of claim 12, in which the means for applying a low bias level comprises a bias source and a large resistor connecting the bias source to the first and second switching transistors; and the means for applying a high bias level comprises a bias turn-on transistor having an emitter and a collector connected in parallel with the large resistor, the sensing means turning on the transistor when the minimum pulse level is exceeded.

Claim 19

The circuitry of claim 15, in which the bias turn-on transistor has a base, the sensing means comprises a resistor and a capacitor connected between the output of one of the switching transistors and the base of the bias turn-on transistor, and a pulldown resistor connected from the base of the bias turn-on transistor to the bias source.

Claim 20

The circuitry of claim 16, in which the sensing means additionally comprises a diode connected in parallel with the pull down resistor.