Patent US4166964A successfully refreshed from Google Patents.
US4166964A
Expired / Lapsed
US
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Inverting buffer circuit
Assignee: RCA Corp
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Filing: 1977-12-08
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Granted: 1979-09-04
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Expires: 1997-12-08
Abstract
Abstract A current source supplies a constant current to a node leading to two parallel branch circuits. The first, comprising a plurality of series connected semiconductor junctions, connects to the input terminal of a current mirror amplifier (CMA) and the second branch circuit comprising the emitter-to-collector path of a transistor, connects to the output terminal of the CMA. An input signal applied to the base of the transistor causes the constant current to steer mainly into the first branch circuit when the signal exceeds a threshold level and mainly into the second branch circuit when the signal is lower than this threshold level. The output signal, which is available at the output terminal of the CMA, comprises a current at a relatively low voltage level which, in one case, is supplied to, and in the other is withdrawn from, the load circuit connected to this terminal.
Inventors
- 👤 Adel A. A. Ahmed
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 07:04
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/01; H03K5/02; H03K19/00; H03K19/0175; H03K19/018; H03K19/01806
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
217 words
A buffer circuit comprising, in combination: a current mirror amplifier having a common terminal connected to a point of reference potential and input and output terminals; a circuit node; a first branch circuit connected between said node and the input terminal of said current mirror amplifier, said first branch circuit including means responsive to current flow therethrough for developing across said branch circuit a voltage at a given level; a second branch circuit connected between said circuit node and said output terminal of said current mirror amplifier, said second branch circuit including the emitter-to-collector path of a transistor, said transistor being connected at its emitter electrode to said node and said transistor having also a base electrode and a base-emitter junction; a buffer circuit input terminal to which an input signal may be applied coupled to said base electrode; a buffer circuit output terminal, at which the buffer circuit output signal is available, at the output terminal of said current mirror amplifier; and a constant current source supplying a constant current to said node, whereby when said input signal is greater than a given threshold level, said constant current steers mainly into said first branch circuit, and when said input signal is lower than a given level, said constant current steers mainly into said second branch circuit.
Claim 2
Dependent Claim
217 words
A buffer circuit comprising, in combination: a current mirror amplifier having a common terminal connected to a point of reference potential and input and output terminals; a circuit node; a first branch circuit connected between said node and the input terminal of said current mirror amplifier, said first branch circuit including means responsive to current flow therethrough for developing across said branch circuit a voltage at a given level; a second branch circuit connected between said circuit node and said output terminal of said current mirror amplifier, said second branch circuit including the emitter-to-collector path of a transistor, said transistor being connected at its emitter electrode to said node and said transistor having also a base electrode and a base-emitter junction; a buffer circuit input terminal to which an input signal may be applied coupled to said base electrode; a buffer circuit output terminal, at which the buffer circuit output signal is available, at the output terminal of said current mirror amplifier; and a constant current source supplying a constant current to said node, whereby when said input signal is greater than a given threshold level, said constant current steers mainly into said first branch circuit, and when said input signal is lower than a given level, said constant current steers mainly into said second branch circuit.
Claim 3
Dependent Claim
29 words
A buffer circuit as set forth in claim 1, wherein said first branch circuit comprises a plurality of semiconductor junctions poled in the same direction connected essentially in series.
Claim 4
Dependent Claim
34 words
A buffer circuit as set forth in claim 2, further including at least one semiconductor junction connected between said input terminal and said base electrode poled in the same direction as said base-emitter junction.
Claim 5
Dependent Claim
34 words
A buffer circuit as set forth in claim 3, wherein said one semiconductor junction comprises the base-emitter junction of a transistor, said transistor having a collector electrode connected to said point of reference potential.
Claim 6
Dependent Claim
62 words
A buffer circuit as set forth in claim 1, further including a load circuit, said load circuit comprising a second current source connected to said output terminal, and a semiconductor junction connected between said second current source and said point of reference potential, said junction being poled in the forward direction relative to the current supplied thereto by said second current source.
Claim 7
Dependent Claim
79 words
A buffer circuit as set forth in claim 2, wherein said first branch circuit comprises a second transistor having base, emitter and collector electrodes and a base-emitter junction, connected at is collector electrode to said circuit node and coupled at its emitter electrode to said input terminal of said current mirror amplifier, and a semiconductor junction connected between said base and said collector electrodes, poled to conduct in the same direction as the base-emitter junction of said second transistor.
Claim 8
Dependent Claim
88 words
A buffer circuit as set forth in claim 1, wherein said first branch circuit comprises N semiconductor junctions connected essentially in series in the forward direction for current flow from said constant current source, and wherein the path between said circuit node and said input terminal includes M semiconductor junctions, including said base-emitter junction, said junctions in said path being connected essentially in series in the forward direction for current flow from said constant current source, where N and M are both integers, N being larger than M.
References Cited (Backward Citations)
US3815037A
Cited
US3872323A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-09-03 | 1983-03-05 | 1983-09-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-09-03 | 1987-03-05 | 1987-09-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-09-03 | 1991-03-05 | 1991-09-04 | $7700.00 | Window Closed / Lapsed |