US4166922A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multi-mode digital enciphering system with repeated priming sequences
Assignee: Datotek Inc
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Filing: 1977-09-09
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Granted: 1979-09-04
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Expires: 1997-09-09
Abstract
Abstract The specification discloses an electronic digital enciphering system which is selectively operable in a plurality of different modes. The system may be operated in an off-line mode for preparing enciphered message tapes prior to transmission via teleprinter message circuits. The system may also be operated in an on-line asynchronous mode wherein a sending station may asynchronously transmit enciphered data on-line to a remote receiving unit, synchronization being provided by the start/stop pulses of the individual digital characters. The system may also be operated in an on-line synchronous mode wherein a sending and a receiving unit are automatically synchronized in time by local self-contained clocks in order to bridge fades or interference in a transmission medium such as radio telegraph, or the like. The system may be utilized on either half-duplex or full-duplex communication channels.
Inventors
- 👤 Frederick A. Kinch, Jr.
- 👤 Barrie O. Morgan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 23:51
CPC Classifications
G; G09; G09C; G09C3/00; H; H04; H04L; H04L9/00; H04L9/06; H04L9/065; H04L9/0656; H04L9/12; H04L2209/00; H04L2209/12; H04L2209/125; H04L2209/34
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
107 words
Prime circuitry for a digital cipher system comprising: a key generator for generating a priming sequence composed of a plurality of random digital prime bits, a storage circuit, means for transmitting said priming sequence to a remote cipher unit and simultaneously to said storage circuit, means for accessing said storage circuit for repetitively transmitting said priming sequence to the remote cipher unit so that said priming sequence is transmitted a predetermined number of times, and said remote cipher unit including receiving means for building a single received sequence with each bit of said received sequence being determined by the corresponding bits of each of said priming sequences.
Claim 2
Dependent Claim
107 words
Prime circuitry for a digital cipher system comprising: a key generator for generating a priming sequence composed of a plurality of random digital prime bits, a storage circuit, means for transmitting said priming sequence to a remote cipher unit and simultaneously to said storage circuit, means for accessing said storage circuit for repetitively transmitting said priming sequence to the remote cipher unit so that said priming sequence is transmitted a predetermined number of times, and said remote cipher unit including receiving means for building a single received sequence with each bit of said received sequence being determined by the corresponding bits of each of said priming sequences.
Claim 3
Dependent Claim
15 words
The prime circuitry of claim 1 wherein said storage circuit comprises a random access memory.
Claim 4
Dependent Claim
16 words
The prime circuitry of claim 1 wherein said priming sequence is transmitted at least five times.
Claim 5
Dependent Claim
14 words
The prime circuitry of claim 1 wherein said priming sequence comprises five binary characters.
Claim 6
Dependent Claim
28 words
The prime circuitry of claim 1 wherein all of said plurality of random digital prime bits are transmitted in their entirety during each of the repeated prime transmissions.
Claim 7
Dependent Claim
47 words
The prime circuitry of claim 1 wherein said means for accessing further comprises: a prime repeat counter for counting the number of repetitive transmissions of said priming sequence, and a transmit prime control for limiting the number of transmissions of said prime sequence to a predetermined number.
Claim 8
Dependent Claim
98 words
The prime circuitry of claim 1 wherein said receiving means comprises: a remote storage circuit of said remote cipher unit for receiving and storing the predetermined number of said priming sequences, an address scan circuit for accessing corresponding bits of each of the predetermined number of said priming sequences stored in said remote storage circuit and for producing groups of corresponding bits, a voting unit for selecting a logic level in response to each group of corresponding bits, and a prime control for producing the received sequence in response to the logic level selected by said voting unit.
Claim 9
Dependent Claim
33 words
The prime circuitry of claim 7 wherein said voting unit selects the logic levels corresponding to the logic level of the greatest number of said corresponding bits in each group of corresponding bits.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-09-03 | 1983-03-05 | 1983-09-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-09-03 | 1987-03-05 | 1987-09-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-09-03 | 1991-03-05 | 1991-09-04 | $7700.00 | Window Closed / Lapsed |