Patent US4165533A successfully refreshed from Google Patents.
US4165533A
Expired / Lapsed
US
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Identification of a faulty address decoder in a function unit of a computer having a plurality of function units with redundant address decoders
Assignee: Telefonaktiebolaget LM Ericsson AB
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Filing: 1977-12-29
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Granted: 1979-08-21
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Expires: 1997-12-29
Abstract
Abstract A central control unit is connected via a common bus system to a number of function units, each of which being furnished with redundant address decoders in order to ensure reliable selection of the function units. If, in response to an address which is sent out by the control unit, a signal is emitted by only one of the two address decoders of a function unit, a recording is made in a memory device corresponding to that decoder to indicate an erroneous condition in one of the address decoders of the addressed function unit. If, on the other hand, signals are emitted by both address decoders a check signal is returned to the control unit, the absence of the check signal indicating that either one of the decoders belonging to the addressed function unit is faulty. Error recordings are read out from the respective memory device by subsequent addressing of the units, the read out from the memory device belonging to the one address decoder being effected by the signal emitted by the other decoder and vice versa.
Inventors
- 👤 Bjorn E. R. Jonsson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 07:17
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/02; G06; G06F; G06F11/00; G06F11/07; G06F11/16; G06F11/1608; G06F11/1616
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
330 words
In a system including a number of addressable function units which are connected to a central control unit via a common bus system and, for safety reasons, are furnished with duplicated address decoders, an apparatus in each of said function units for identifying a faulty address decoder in one function unit which is operated when another function unit was actually addressed, said apparatus comprising in each function unit an arrangement of logic circuits being connected to the outputs of the two address decoders of the function unit and being arranged to supply three indication signals; a first indication signal when only the first one of said two address decoders has detected a certain address being sent from the central control unit, a second indication signal when only the second one of said two address decoders has detected said certain address and a third indication signal when both of said two address decoders have detected said certain address; first and second bistable recording means being set by said first and second indication signal, respectively; a first reading logic circuit controlled by the second one of said two address decoders for reading out a recording made in said first recording means upon detection of said certain address; a second reading logic circuit controlled by the first one of said two address decoders for reading out a recording made in said second recording means upon detection of said certain address; first and second output means for transferring to said common bus system the readings from said first and second reading logic circuits, respectively; and a third reading logic circuit connected to both of said address decoders for transferring to said common bus system said third indication signal when both address decoders are activated simultaneously but later than said first or second reading logic circuit if its associated recording means has been previously set due to a fault, said recording means having reset inputs connected to the output of said third reading logic circuit.
Claim 2
Dependent Claim
330 words
In a system including a number of addressable function units which are connected to a central control unit via a common bus system and, for safety reasons, are furnished with duplicated address decoders, an apparatus in each of said function units for identifying a faulty address decoder in one function unit which is operated when another function unit was actually addressed, said apparatus comprising in each function unit an arrangement of logic circuits being connected to the outputs of the two address decoders of the function unit and being arranged to supply three indication signals; a first indication signal when only the first one of said two address decoders has detected a certain address being sent from the central control unit, a second indication signal when only the second one of said two address decoders has detected said certain address and a third indication signal when both of said two address decoders have detected said certain address; first and second bistable recording means being set by said first and second indication signal, respectively; a first reading logic circuit controlled by the second one of said two address decoders for reading out a recording made in said first recording means upon detection of said certain address; a second reading logic circuit controlled by the first one of said two address decoders for reading out a recording made in said second recording means upon detection of said certain address; first and second output means for transferring to said common bus system the readings from said first and second reading logic circuits, respectively; and a third reading logic circuit connected to both of said address decoders for transferring to said common bus system said third indication signal when both address decoders are activated simultaneously but later than said first or second reading logic circuit if its associated recording means has been previously set due to a fault, said recording means having reset inputs connected to the output of said third reading logic circuit.
Claim 3
Dependent Claim
148 words
In a system including a plurality of addressable function units connected to a central control unit via a common bus system, each of the function units having a pair of redundant address decoders receiving addresses on the common bus system, the method of indicating that an address decoder in one function unit erroneously decoded the address of another function unit comprising, in any function unit, the steps of storing an indication when only one of the address decoders therein decodes an address, thereafter whenever the other of the address decoders decodes an address determining whether there is stored an indication that said one address decoder had previously decoded an address, and if said indication is stored, signalling the central control unit of such storage whereby the central control unit is informed that one of the address decoders in the function unit then being addressed had previously operated erroneously.
Claim 4
Dependent Claim
148 words
In a system including a plurality of addressable function units connected to a central control unit via a common bus system, each of the function units having a pair of redundant address decoders receiving addresses on the common bus system, the method of indicating that an address decoder in one function unit erroneously decoded the address of another function unit comprising, in any function unit, the steps of storing an indication when only one of the address decoders therein decodes an address, thereafter whenever the other of the address decoders decodes an address determining whether there is stored an indication that said one address decoder had previously decoded an address, and if said indication is stored, signalling the central control unit of such storage whereby the central control unit is informed that one of the address decoders in the function unit then being addressed had previously operated erroneously.
Claim 5
Dependent Claim
28 words
The method of claim 2 further comprising the step of cancelling the stored indication after said signalling step whenever both of the address decoders simultaneously decoded an address.
Claim 6
Dependent Claim
26 words
The method of claim 2 further comprising the step of signalling the central control unit when both of the address decoders simultaneously decode the same address.
Claim 7
Dependent Claim
26 words
The method of claim 3 further comprising the step of signalling the central control unit when both of the address decoders simultaneously decode the same address.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-08-20 | 1983-02-19 | 1983-08-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-08-20 | 1987-02-19 | 1987-08-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-08-20 | 1991-02-19 | 1991-08-21 | $7700.00 | Window Closed / Lapsed |