Patent US4163944A successfully refreshed from Google Patents.
US4163944A
Expired / Lapsed
US
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Compensation circuit for an electrical signal mixer
Assignee: Raytheon Co
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Filing: 1976-12-22
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Granted: 1979-08-07
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Expires: 1996-12-22
Abstract
Abstract The carrier suppression circuit of the present invention is utilized to minimize electrical imbalances within double-balanced mixers. The circuit operates upon a modulating signal, having at least two states so as to adjust the dwell time that the signal stays in a particular state to counteract the effects of electrical imbalance within the mixer. Minimization of the electrical imbalance provides a greater suppression of the carrier signal which, in turn, improves the quality of the signal both at the transmitter and at the receiver.
Inventors
- 👤 Ramon P. Chambers
- 👤 Robert S. Gordy
- 👤 David E. Sanders
- 👤 Cameron E. Morrison
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 09:17
CPC Classifications
H; H03; H03C; H03C1/00; H03C1/52; H03C1/54; H04; H04B; H04B7/00; H04B7/005
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
105 words
A compensating circuit for an electrical mixer comprising: a double-balanced mixer having first and second inputs, said first input adapted to receive an input signal; a modulating signal source for providing a modulating signal having at least two states; adjustable delay means responsive to a synchronizing component of said modulating signal for providing first and second adjustable delayed synchronizing signal components, corresponding to respective states of said modulating signal; and means responsive to said provided delayed signal for operatively connecting said provided modulating signal to said double-balanced mixer such that the electrical imbalance in said double-balanced mixer is minimized by adjusting said adjustable delay means.
Claim 2
Dependent Claim
105 words
A compensating circuit for an electrical mixer comprising: a double-balanced mixer having first and second inputs, said first input adapted to receive an input signal; a modulating signal source for providing a modulating signal having at least two states; adjustable delay means responsive to a synchronizing component of said modulating signal for providing first and second adjustable delayed synchronizing signal components, corresponding to respective states of said modulating signal; and means responsive to said provided delayed signal for operatively connecting said provided modulating signal to said double-balanced mixer such that the electrical imbalance in said double-balanced mixer is minimized by adjusting said adjustable delay means.
Claim 3
Dependent Claim
19 words
The compensation circuit according to claim 1 wherein said modulating signal source provides a linear pseudo-random sequence of pulses.
Claim 4
Dependent Claim
139 words
A compensation circuit for an electrical mixer comprising: a mixer means having at least a first and a second input, said first input adapted to receive an input signal; generating means for generating a pseudo-random sequence signal having at least two states; a clock input adapted to receive a clocking signal; gating means for operatively connecting said second input of said mixer means to said generating means in response to the clocking signal received at said clock input; and re-clocking means operatively connected to said gating means and responsive to the states of said pseudo-random sequence signal for providing a re-clocking signal for controlling said gating means so as to adjust the amount of time said pseudo-random sequence signal is applied to said mixer means in each of said states to minimize the electrical imbalances of said mixer means.
Claim 5
Dependent Claim
139 words
A compensation circuit for an electrical mixer comprising: a mixer means having at least a first and a second input, said first input adapted to receive an input signal; generating means for generating a pseudo-random sequence signal having at least two states; a clock input adapted to receive a clocking signal; gating means for operatively connecting said second input of said mixer means to said generating means in response to the clocking signal received at said clock input; and re-clocking means operatively connected to said gating means and responsive to the states of said pseudo-random sequence signal for providing a re-clocking signal for controlling said gating means so as to adjust the amount of time said pseudo-random sequence signal is applied to said mixer means in each of said states to minimize the electrical imbalances of said mixer means.
Claim 6
Dependent Claim
75 words
The compensating circuit according to claim 3 wherein said gating means is comprised of: a first flip-flop means having a data input for receiving said pseudo-random sequence signal and a clocking input for receiving said clocking signal; and a second flip-flop means having a data input for receiving the output from said first flip-flop means and a clocking input responsive to said re-clocking signal for operatively connecting said pseudo-random sequence signal to said mixer means.
Claim 7
Dependent Claim
22 words
The compensating circuit according to claim 3 and further comprising: a driver means interposed between said gating means and said mixer means.
Claim 8
Dependent Claim
15 words
The compensating circuit according to claim 3 wherein said mixer means is a double-balanced mixer.
Claim 9
Dependent Claim
210 words
A compensation circuit for an electrical mixer comprising: a mixer means having at least a first and a second input, said first input adapted to receive an input signal; generating means for generating a pseudo-random sequence signal having at least two states; a clock input adapted to receive a clocking signal; gating means for operatively connecting said second input of said mixer means to said generating means in response to the clocking signal received at said clock input; and re-clocking means operatively connected to said gating means comprising: a first delay means operatively connected to said clock input for delaying the clocking signal by a first delay; a second delay means operatively connected to said clock input for delaying the clocking signal by a second delay, wherein the difference between said first and said second delay corresponds to a time adjustment; and switch means responsive to the states of said pseudo-random sequence signal for selecting the delayed signal from said first or said second delay means, so as to provide a re-clocking signal for controlling said gating means so as to adjust the amount of time said pseudo-random sequence signal is applied to said mixer means in each of said states to minimize the electrical imbalances of said mixer means.
Claim 10
Dependent Claim
210 words
A compensation circuit for an electrical mixer comprising: a mixer means having at least a first and a second input, said first input adapted to receive an input signal; generating means for generating a pseudo-random sequence signal having at least two states; a clock input adapted to receive a clocking signal; gating means for operatively connecting said second input of said mixer means to said generating means in response to the clocking signal received at said clock input; and re-clocking means operatively connected to said gating means comprising: a first delay means operatively connected to said clock input for delaying the clocking signal by a first delay; a second delay means operatively connected to said clock input for delaying the clocking signal by a second delay, wherein the difference between said first and said second delay corresponds to a time adjustment; and switch means responsive to the states of said pseudo-random sequence signal for selecting the delayed signal from said first or said second delay means, so as to provide a re-clocking signal for controlling said gating means so as to adjust the amount of time said pseudo-random sequence signal is applied to said mixer means in each of said states to minimize the electrical imbalances of said mixer means.
Claim 11
Dependent Claim
248 words
A compensation circuit for an electrical mixer comprising: a mixer means having at least a first and a second input, said first input adapted to receive an input signal; generating means for generating a pseudo-random sequence signal having at least two states; a clock input adapted to receive a clocking signal; gating means for operatively connecting said second input of said mixer means to said generating means in response to the clocking signal received at said clock input; and re-clocking means operatively connected to said gating means comprising: a first delay means operatively connected to said clock input for delaying the clocking signal by a first delay; a second delay means operatively connected to said clock input for delaying the clocking signal by a second delay, wherein the difference between said first and said second delay corresponds to a time adjustment; and switch means comprising: a first NAND gate for receiving as inputs the signals from said first delay means and said generating means; a second NAND gate for receiving as inputs the signal from said second delay means and the complement of said pseudo-random sequence signal; and a third NAND gate for receiving as inputs the signals from said first and said second NAND gate to provide a re-clocking signal for controlling said gating means so as to adjust the amount of time said pseudo-random sequence signal is applied to said mixer means in each of said states to minimize the electrical imbalances of said mixer means.
Claim 12
Dependent Claim
248 words
A compensation circuit for an electrical mixer comprising: a mixer means having at least a first and a second input, said first input adapted to receive an input signal; generating means for generating a pseudo-random sequence signal having at least two states; a clock input adapted to receive a clocking signal; gating means for operatively connecting said second input of said mixer means to said generating means in response to the clocking signal received at said clock input; and re-clocking means operatively connected to said gating means comprising: a first delay means operatively connected to said clock input for delaying the clocking signal by a first delay; a second delay means operatively connected to said clock input for delaying the clocking signal by a second delay, wherein the difference between said first and said second delay corresponds to a time adjustment; and switch means comprising: a first NAND gate for receiving as inputs the signals from said first delay means and said generating means; a second NAND gate for receiving as inputs the signal from said second delay means and the complement of said pseudo-random sequence signal; and a third NAND gate for receiving as inputs the signals from said first and said second NAND gate to provide a re-clocking signal for controlling said gating means so as to adjust the amount of time said pseudo-random sequence signal is applied to said mixer means in each of said states to minimize the electrical imbalances of said mixer means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-08-06 | 1983-02-05 | 1983-08-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-08-06 | 1987-02-05 | 1987-08-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-08-06 | 1991-02-05 | 1991-08-07 | $7700.00 | Window Closed / Lapsed |