System for reducing band width of image signal

Claim 3

A system as claimed in claim 1, wherein said circuit means for logically summing the bit signals of the picture elements on the scanning lines comprises an OR circuit.

Claim 4

A system as claimed in claim 1, wherein said logically summing circuit means comprises a NOR circuit.

Claim 5

A system as claimed in claim 1 including scanning means for scanning the information to be processed and sampling and quantizing it; first memory means connected to said scanning means for storing information of a first scanning line and for reading out one of information of the first scanning line when every one information of the scanning line is read in; OR circuit means connected to the output of said first memory means; discriminator means connected to the output of said OR circuit means for determining whether said output of said OR circuit means comprises a signal in an 0 section or 1 section; mode transition detecting means with input connected to the output of said OR circuit means for comparing the code of the output signal of said OR circuit means and detecting whether a coincidence signal or mode transition is generated; counter and run length coding circuit means for counting the number of pulses when one pulse is transmitted in case of a signal corresponding to the 0 section and for run length coding; second memory means with one input connected to said OR circuit means and a second input connected to the output of said first memory means for storing an information of a picture element at the present scanning position in section 1 of an information of a picture element at the same position as that of the first scanning line in predetermined sequence; said counter means coding the counted run length by the run length code and transmitting the result to said OR circuit means when a mode transition is detected; said second memory circuit means storing two picture element informations of the first and second scanning lines; said second memory means transmits the stored information in section 1 of the OR signal and transmits an end signal simultaneously when a mode transition is generated from the section 0 of the OR signal to the section 1; and buffer memory means connected to the output of said OR circuit means for transmitting information to a transmission line at a predetermined transmission speed.

Claim 6

A system as claimed in claim 1, wherein said coding circuit means comprises means for run length-coding one of said sections, and means for converting the other section into a series of raw signals by arranging sequentially the bit signals in the same position as in the original signals and into an end signal positioned at the end of the raw signal train for signalling the termination of the raw signal train.

Claim 7

A system as claimed in claim 5, wherein said end signal for indicating the boundary of the raw signal train and series of run length codes consists of binary signals, the number of which is made the same as that of said scanning lines.