Patent US4161787A successfully refreshed from Google Patents.
US4161787A
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Programmable timer module coupled to microprocessor system
Assignee: Motorola Solutions Inc
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Filing: 1977-11-04
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Granted: 1979-07-17
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Expires: 1997-11-04
Abstract
Abstract A programmable timer module (PTM) is provided as a component of a microprocessor system in order to generate and measure varying time intervals under program control. The programmable timer module includes, in one embodiment, three independent 16-bit timers. Each timer includes a 16-bit counter and a 16-bit latch. The programmable timer module also includes an 8-bit status register and an 8-bit control register each of which may be coupled to an 8-bit bidirectional data bus of a microprocessor system. Selection circuitry is provided which permits the microprocessor to select either the control register or the status register. Information can be written into the control register; the operation is effected by means of read/write circuitry and a read/write input. Any one of the three timers can also be selected by means of the selection circuitry, and a 16-bit number can be written into the selected 16-bit latch. Reset circuitry resets the counter whenever the 16-bit latch is written into, and the counter counts until it reaches the number written into the 16-bit latch, whereupon the interrupt circuitry generates an interrupt signal and sets an appropriate interrupt bit in the status register, and also resets that counter. The counter continues counting at the appropriate clock rate after the interrupt so that time since the interrupt may be determined by the microprocessor. The outputs of the three counters can be selected as outputs of the programmable timer module.
Inventors
- 👤 Stanley E. Groves
- 👤 Gene A. Schriber
- 👤 Brian M. Spinks
- 👤 Richard M. Baker
- 👤 Thomas C. Daly
- 👤 Rodney J. Means
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 21:31
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/0703; G06F11/0751; G06F11/0754; G06F11/0757; G06F1/00; G06F1/04; G06F1/14
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
185 words
A programmable timer device for use within a digital processing system and coupleable to a data bus of said system and responsive to a clock signal, comprising: latch means responsive to signals on said data bus for receiving and storing a first binary number from said data bus; counter means responsive to said clock signal coupled to said latch means and to said data bus for counting at a rate determined by said clock signal; first means coupled to said latch means and said counter means for generating a signal for interrupting the operation of the system in response to a matching between the contents of said counter means and said first binary number; status storage means responsive to said first means coupled to said data bus for storing information indicative of the occurrence of said interrupt signal; for receiving selection signals; selection means responsive to said selection signals coupled to said latch mean, said counter means, and said status storage means for selectively and operatively coupling a one of said latch means, said status storage means, and said counter means to said data bus.
Claim 2
Dependent Claim
185 words
A programmable timer device for use within a digital processing system and coupleable to a data bus of said system and responsive to a clock signal, comprising: latch means responsive to signals on said data bus for receiving and storing a first binary number from said data bus; counter means responsive to said clock signal coupled to said latch means and to said data bus for counting at a rate determined by said clock signal; first means coupled to said latch means and said counter means for generating a signal for interrupting the operation of the system in response to a matching between the contents of said counter means and said first binary number; status storage means responsive to said first means coupled to said data bus for storing information indicative of the occurrence of said interrupt signal; for receiving selection signals; selection means responsive to said selection signals coupled to said latch mean, said counter means, and said status storage means for selectively and operatively coupling a one of said latch means, said status storage means, and said counter means to said data bus.
Claim 3
Dependent Claim
57 words
The programmable timer device as recited in claim 1 further comprising: a read-write input for receiving a read-write signal; read-write means responsive to said read-write signal coupled to said latch means and to said status storage means for enabling transfer of said first binary number from said data bus to said latch means during a write cycle.
Claim 4
Dependent Claim
48 words
The programmable timer device as recited in claim 2 wherein said read-write means further includes means responsive to said read-write signal coupled to said data bus and to said counter means for effecting transfer of contents of said counter means to said data bus during a write cycle.
Claim 5
Dependent Claim
44 words
The programmable timer device as recited in claim 2 further comprising means responsive to said latch means and to said counter means for resetting said counter means in response to a matching between the contents of said counter means and said first binary number.
Claim 6
Dependent Claim
66 words
The programmable timer device as recited in claim 4 further comprising: control storage means responsive to said data bus for storing control information received from said data bus; interrupt means responsive to said control storage means and to said interrupt signal for producing an interrupt output signal in response to said interrupt signal conditioned upon the presence of said control information in said control storage means.
Claim 7
Dependent Claim
58 words
The programmable timer device as recited in claim 5 further comprising: an output; output means responsive to said counter means and to said output for conditionally causing an output voltage on said output to toggle in response to the time out of said counter means of said first binary number, conditioned on information in said control storage means.
Claim 8
Dependent Claim
33 words
The programmable timer device as recited in claim 4 further comprising means responsive to said read-write input for resetting said counter means in response to a write signal applied to said read-write input.
Claim 9
Dependent Claim
258 words
A programmable timer device for use within a digital processing system and responsive to a clock signal and coupleable to a data bus of said system, comprising: first latch means responsive to said data bus for receiving and storing a first binary number from said data bus; second latch means responsive to said data bus for receiving and storing a second binary number from said data bus; first counter means responsive to said clock signal for counting at a rate determined by said clock signal; second counter means responsive to said first counter means for counting at a rate determined by said first counter means; first means responsive to said first latch means and to said first counter means for resetting said first counter means in response to a match between the contents of said first counter means and said first binary number; second means responsive to said second counter means and to said second latch means for resetting said second counter means in response to a matching of the contents of said second counter means with said second binary number; third means responsive to said first counter means for incrementing or decrementing said second counter means in response to said matching between the contents of said first counter means and said first binary number; fourth means responsive to said second counter means and to said second latch means for generating a signal for interrupting the operation of the system in response to said matching between the contents of said second counter means and said second binary number.
Claim 10
Dependent Claim
258 words
A programmable timer device for use within a digital processing system and responsive to a clock signal and coupleable to a data bus of said system, comprising: first latch means responsive to said data bus for receiving and storing a first binary number from said data bus; second latch means responsive to said data bus for receiving and storing a second binary number from said data bus; first counter means responsive to said clock signal for counting at a rate determined by said clock signal; second counter means responsive to said first counter means for counting at a rate determined by said first counter means; first means responsive to said first latch means and to said first counter means for resetting said first counter means in response to a match between the contents of said first counter means and said first binary number; second means responsive to said second counter means and to said second latch means for resetting said second counter means in response to a matching of the contents of said second counter means with said second binary number; third means responsive to said first counter means for incrementing or decrementing said second counter means in response to said matching between the contents of said first counter means and said first binary number; fourth means responsive to said second counter means and to said second latch means for generating a signal for interrupting the operation of the system in response to said matching between the contents of said second counter means and said second binary number.
Claim 11
Dependent Claim
100 words
The programmable timer device are recited in claim 8 further comprising: an output; output means responsive to said first counter means and to said second counter means coupled to said output for causing an output voltage on said output to toggle in one direction in response to a matching between the contents of said first counter means and said first binary number and to toggle in an opposite direction in response to the combination of a matching between the contents of said first counter means and said first binary number and said second counter means and said second binary number.
References Cited (Backward Citations)
US3434115A
Cited
US3573751A
Cited
US3742463A
Cited
US3771144A
Cited
US3862372A
Cited
US3891973A
Cited
US3969703A
Cited
US4063308A
Cited
US4024510A
Cited
US4034352A
Cited
US4025768A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-07-16 | 1983-01-15 | 1983-07-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-07-16 | 1987-01-15 | 1987-07-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-07-16 | 1991-01-15 | 1991-07-17 | $7700.00 | Window Closed / Lapsed |