Semiconductor devices and circuit arrangements including such devices

Claim 2

A semiconductor device formed in a semiconductor body comprising a substrate of one conductivity type, a thin layer initially wholly of said one conductivity type disposed on said substrate of the same conductivity type, said device having a plurality of constituent components, at least one of the components including a combination of regions comprising a buried layer of said opposite conductivity type at a portion of the interface between the thin layer and the substrate, and an isolation barrier for the component of said opposite conductivity type, the isolation barrier extending through the thin layer to the buried layer, regions of the device and of said one conductivity type extending beyond said at least one component, but contiguous with said at least one component, and said at least one component including at least one outer annular region of said opposite conductivity type, said annular region being disposed adjacent to the surface of the thin layer remote from the substrate, and being uniformly spaced from the combination of regions of said at least one component, and a significant resistance region between said at least one outer annular region and the combination of regions of said at least one component, said significant resistance region being a part of the component.

Claim 3

A semiconductor device as claimed in claim 1 in which the resistance of the resistive region of said at least one component is such that the breakdown potential difference between the combination of regions of said at least one component, and the regions of the device beyond, but contiguous with, said at least one component, can be at least 10 volts.

Claim 4

A semiconductor device as claimed in claim 1 in which means is provided whereby a potential difference can be provided between at least two spaced points of the device, so that a potential difference can be provided between the combination of regions of said at least one component, and the regions of the device beyond, but contiguous with, said at least one component.

Claim 5

A semiconductor device as claimed in claim 3 in which the means, whereby a potential difference can be provided between at least two spaced points of the device, at least includes a contact to the substrate of the semiconductor body, and a contact to the combination of regions of said at least one component.

Claim 6

A semiconductor device as claimed in claim 1 in which means is provided for removing breakdown current flowing between the combination of regions of said at least one component, and the regions of the device beyond, but contiguous with, said at least one component.

Claim 7

A semiconductor device as claimed in claim 5 in which the means provided for removing breakdown current includes a contact provided on the substrate of the semiconductor body.

Claim 8

A semiconductor device as claimed in claim 1 in which said at least one component is operably connected to at least one other component having a combination of regions comprising a buried layer of the opposite conductivity type at a portion of the interface between the thin layer and the substrate, and an isolation barrier of the opposite conductivity type for said at least one other component, the isolation barrier extending through the thin layer to the buried layer.

Claim 9

A semiconductor device as claimed in claim 1 in which a heavily doped portion of said one conductivity type is provided, adjacent to the surface of the thin layer remote from the substrate, in each region of the device within the thin layer, and of said one conductivity type.

Claim 10

A semiconductor device as claimed in claim 1 in which the thin layer is an epitaxial layer.

Claim 11

A semiconductor device as claimed in claim 1 in which a region of the device of said one conductivity type, and within the thin layer, is between said at least one component and each other component of the device.

Claim 12

A semiconductor device as claimed in claim 1 in which said at least one outer annular region of said at least one component does not extend to the interface between the thin layer and the substrate.

Claim 13

A semiconductor device as claimed in claim 11 in which, when the device is considered in plan, the buried layer of the combination of regions of said at least one component extends to be directly opposite, but is spaced from, at least part of said at least one outer annular region of the component.

Claim 14

A semiconductor device as claimed in claim 1 in which said at least one outer annular region of said at least one component extends to the interface between the thin layer and the substrate, and includes a buried layer at the interface.

Claim 15

A semiconductor device as claimed in claim 13 in which, when the device is considered in plan, the buried layer of the combination of regions of said at least one component extends beyond the isolation barrier.

Claim 16

A semiconductor device as claimed in claim 14 in which, when the device is considered in plan, the buried layer of said at least one outer annular region, at the interface between the thin layer and the substrate, extends beyond the remainder of said at least one outer annular region, and towards the combination of regions.

Claim 17

A semiconductor device as claimed in claim 1 in which a connection is provided between said at least one outer annular region and the surface portion of the region between said at least one outer annular region and the isolation barrier of said at least one component, so that the component parts connected together are maintained at a common potential level.

Claim 18

A semiconductor device as claimed in claim 16 in which the connection comprises a contact spanning a surface portion of the P-N junction between said at least one outer annular region and the region between said at least one outer annular region and the isolation barrier.

Claim 19

A semiconductor device as claimed in claim 1 in which a plurality of spaced, outer annular regions are provided in said at least one component adjacent to the surface of the thin layer remote from the substrate, and the plurality of outer annular regions being uniformly spaced from each other, a resistive component part being provided between each outer annular region and the combination of regions of said at least one component.

Claim 20

A semiconductor device as claimed in claim 18 in which a resistive component part is provided between each adjacent pair of outer annular regions.

Claim 21

A circuit arrangement, at least partially embodied in a semiconductor device, in a semiconductor body comprising a substrate of one conductivity type, a thin layer initially wholly of said one conductivity type disposed on said substrate of the same conductivity type, said device having a plurality of constituent components, at least one of the components including a combination of regions comprising a buried layer of said opposite conductivity type at a portion of the interface between the thin layer and the substrate, and an isolation barrier of said opposite conductivity type for the component, the isolation barrier extending through the thin layer to the buried layer, there being regions of the device and of said one conductivity type beyond said at least one component, but contiguous with said at least one component, and said at least one component including at least one outer annular region of said opposite conductivity type, said annular region being disposed adjacent to the surface of the thin layer remote from the substrate, and being uniformly spaced from the combination of regions, of said at least one component, and a significant resistance region between said at least one outer annular region and the combination of regions of at said at least one component, said significant resistance region being at least a portion of a part of the component, and the circuit arrangement also including means to maintain at least two spaced points of the device at different potential levels, the circuit arrangement being such that the potential level of at least one of the constitutent parts of said at least one component of the device comprising said at least one outer annular region and the combination of regions, is intermediate between the potential level of the combination of regions and the potential level of the regions of the device beyond, but contiguous with, said at least one component.

Claim 22

A circuit arrangement, at least partially embodied in a semiconductor device, in a semiconductor body comprising a substrate of one conductivity type, a thin layer initially wholly of said one conductivity type disposed on said substrate of the same conductivity type, said device having a plurality of constituent components, at least one of the components including a combination of regions comprising a buried layer of said opposite conductivity type at a portion of the interface between the thin layer and the substrate, and an isolation barrier of said opposite conductivity type for the component, the isolation barrier extending through the thin layer to the buried layer, there being regions of the device and of said one conductivity type beyond said at least one component, but contiguous with said at least one component, and said at least one component including at least one outer annular region of said opposite conductivity type, said annular region being disposed adjacent to the surface of the thin layer remote from the substrate, and being uniformly spaced from the combination of regions, of said at least one component, and a significant resistance region between said at least one outer annular region and the combination of regions of at said at least one component, said significant resistance region being at least a portion of a part of the component, and the circuit arrangement also including means to maintain at least two spaced points of the device at different potential levels, the circuit arrangement being such that the potential level of at least one of the constitutent parts of said at least one component of the device comprising said at least one outer annular region and the combination of regions, is intermediate between the potential level of the combination of regions and the potential level of the regions of the device beyond, but contiguous with, said at least one component.

Claim 23

A circuit arrangement as claimed in claim 20 and in which a potential difference of at least 10 volts is applied between said at least two spaced points of the device to be maintained at different potential levels.

Claim 24

A circuit arrangement as claimed in claim 20 and in which a potential difference of at least 10 volts is applied between the combination of regions of said at least one component, and the regions of the device boyond, but contiguous with, said at least one component.

Claim 25

A circuit arrangement as claimed in claim 20 in which means is provided whereby at least one of the constituent parts of said at least one component of the device comprising said at least one outer annular region, and the surface portion of the region between said at least one outer annular region and the combination of regions, is maintained at a predetermined potential level intermediate between the potential level of the combination of regions, and the potential level of the regions of the device beyond, and contiguous with said at least one component.

Claim 26

A circuit arrangement as claimed in claim 23 in which said predetermined potential level is mid-way between the potential level of the combination of regions and the potential level of the regions of the device beyond, but contiguous with, said at least one component.

Claim 27

A circuit arrangement as claimed in claim 23 in which said at least one outer annular region, and the surface portion of the region between said at least one outer annular region and the combination of regions, of said at least one component, are maintained at the same predetermined potential level.

Claim 28

A circuit arrangement as claimed in claim 20 and in which means is provided for removing breakdown current flowing between the combination of regions of said at least one component, and the regions of the device beyond, but contiguous with, said at least one component, the means including a contact provided on the substrate of the semiconductor body, the circuit arrangement also including a potential source connected to the contact, to maintain the contact at an appropriate potential level.

Claim 29

A circuit arrangement as claimed in claim 20 and in which said at least one component is operably connected to at least one other component of the device, said at least one other component having a combination of regions comprising a buried layer of the opposite conductivity type at a portion of the interface between the thin layer and the substrate, and an isolation barrier of the opposite conductivity type for said at least one other component, the isolation barrier extending through the thin layer to the buried layer, the circuit arrangement being such that a larger potential difference is provided between the combination of regions of said at least one component, and the regions of the device beyond, and contiguous with, said at least one component, compared with the potential difference provided between the combination of regions of said at least one other component, and the regions of the device beyond, and contiguous with, said at least one other component.

Claim 30

A circuit arrangement as claimed in claim 20 and in which a plurality of spaced, outer annular regions are provided in said at least one component adjacent to the surface of the thin layer remote from the substrate, the plurality of outer annular regions being uniformly spaced from each other, a resistive component part being provided between each outer annular region and the combination of regions of said at least one component, and each outer annular region is maintained at a predetermined potential level intermediate between the potential level of the regions of th e device beyond the component and contiguous with the component, the potential differences between each of the outer annular regions and the combination of regions increasing as the distances between the outer annular regions and the combination of regions increases.