US4160984A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Schottky-gate field-effect transistor and fabrication process therefor
Assignee: Raytheon Co
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Filing: 1977-11-14
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Granted: 1979-07-10
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Expires: 1997-11-14
Abstract
Abstract The specification describes a Schottky-gate field-effect transistor and related fabrication process wherein thin ion implanted surface stabilization regions are formed between source and gate electrodes and gate and drain electrodes of the device and to a thickness of between 100 and 1,000 angstroms. This is accomplished utilizing the source, gate and drain electrodes as an ion implantation mask against impinging inert ions which render the implanted regions semi-insulating, and this process requires no post-implantation annealing.
Inventors
- 👤 Glenn O. Ladd, Jr.
- 👤 Frederick W. Cleary
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 23:31
CPC Classifications
H; H10; H10P; H10P30/00; H10P30/20; H10P30/202; H10P30/206; H10D; H10D30/00; H10D30/80; H10D30/87; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/161; H10P30/208
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
88 words
A Schottky-gate field-effect transistor which comprises a III-V compound semiconductor crystal having spaced apart source, gate and drain electrodes thereof defining active current path regions of said device and further including thin inert ion implanted and lattice damaged high resistivity or semi-insulating regions extending only between and laterally coextensive with the spacing between said gate and source and said gate and drain electrodes, respectively, of said device and into said crystal to a depth of 1,000 angstroms or less to thereby minimize device drift, time constants and noise.
Claim 2
Dependent Claim
88 words
A Schottky-gate field-effect transistor which comprises a III-V compound semiconductor crystal having spaced apart source, gate and drain electrodes thereof defining active current path regions of said device and further including thin inert ion implanted and lattice damaged high resistivity or semi-insulating regions extending only between and laterally coextensive with the spacing between said gate and source and said gate and drain electrodes, respectively, of said device and into said crystal to a depth of 1,000 angstroms or less to thereby minimize device drift, time constants and noise.
Claim 3
Dependent Claim
90 words
The device defined in claim 1 wherein said semiconductor crystal includes a substrate with an epitaxial semiconductor layer thereon, with the surface of said epitaxial semiconductor layer between said source and drain electrodes being contoured in a trapezoidial inverted mesa configuration wherein a horizontal mesa surface thereof supports said gate electrode in close proximity to an epitaxial layer-substrate interface of said device, and said inert ion implanted regions extend over the contoured sides of said inverted mesa configuration and only between said source and gate and gate and drain electrodes.
Claim 4
Dependent Claim
50 words
The device defined in claim 1 wherein the bulk resistivity of said ion implanted regions is in the range of 10 4 -10 8 ohm·centimeters, and said ion implanted regions represent less than 50 precent of the total thickness of the gallium arsenide epitaxial layer in which they are located.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-07-09 | 1983-01-08 | 1983-07-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-07-09 | 1987-01-08 | 1987-07-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-07-09 | 1991-01-08 | 1991-07-10 | $7700.00 | Window Closed / Lapsed |