Magnetic bubble memory chip synchronization and redundancy

Claim 2

A magnetic domain memory structure comprising: a layer of magnetic material capable of supporting magnetic domains; said layer of magnetic material being organized into open ended first and second major propagation paths suitably positioned adjacent to and operatively associated with a plurality of minor loops for storing said magnetic domains; means for generating magnetic domains connected to said first major propagation paths; transfer means for moving said magnetic domains from said first major propagation paths to said plurality of minor loops; replicate means disposed between said plurality of minor loops and said second major propagation paths for transferring magnetic domains from said minor loops to said second major propagation paths; means for detecting the presence of magnetic domains connected to and operatively associated with said second major propagation paths; and a dedicated minor loop disposed adjacent to said plurality of minor loops, for storing synchronization and redundancy data.

Claim 3

A magnetic domain memory structure as set forth in claim 1, wherein said means for detecting magnetic domains comprises an active detector means for sensing magnetic domains and a dummy detector means for canceling noise caused by the rotating magnetic field.

Claim 4

A magnetic domain memory structure as set forth in claim 1, further including an annihilate means for destroying magnetic domains connected to said first major propagation paths.

Claim 5

A magnetic domain memory structure as set forth in claim 1, wherein said annihilate means comprises a permanent magnet having a polarity opposite to the polarity of said magnetic domains.

Claim 6

A magnetic domain memory structure as set forth in claim 1, wherein said synchronization data comprises a predetermined sequence of magnetic domains.

Claim 7

A magnetic domain memory structure as set forth in claim 1, wherein said redundancy data comprises a predetermined sequence of magnetic domains for locating defective minor loops.

Claim 8

A magnetic domain memory structure as set forth in claim 1, wherein said dedicated minor loop is write accessed by a separate second transfer means.

Claim 9

A magnetic domain memory structure as set forth in claim 1, wherein said dedicated minor loop is read accessed by a separate second replicate means.

Claim 10

A magnetic domain memory structure as set forth in claim 1, further including a second plurality of minor loops located in spaced parallel relation to said plurality of minor loops.

Claim 11

A magnetic domain memory structure as set forth in claim 9, wherein said plurality of minor loops and said second plurality of minor loops are each disposed adjacent to a said first major propagation path having generator means connected thereto.

Claim 12

A magnetic domain memory structure as set forth in claim 9, wherein said plurality of minor loops and said second plurality of minor loops are each disposed in a perpendicular fashion adjacent to a said second major propagation path.

Claim 13

A magnetic domain memory structure as set forth in claim 10, wherein both of said second major propagation paths merge into one path for transporting magnetic domains to said detector means.

Claim 14

A magnetic domain memory system comprising: a data chip including; a thin magnetic film suitable for use in generating magnetic domains, said layer of magnetic material being organized into open ended first and second major propagation paths suitably positioned adjacent to and operatively associated with a plurality of minor loops for storing said magnetic domains, transfer means for moving said magnetic domains from said first major propagation paths to said plurality of minor loops, replicate means disposed between said plurality of minor loops and said second major propagation paths for transferring magnetic domains from said minor loops to said second major propagation paths. means for detecting the presence of magnetic domains connected to and operatively associated with said second major propagation paths, dedicated minor loop disposed in parallel relation to said plurality of minor loops, for storing synchronization and redundancy data; and control means for propagating first and second magnetic domains around each of said major propagation paths and around said minor loops at a selected clock frequency and controlling transfer of magnetic domains between said minor loops and said first and second major propagation paths.

Claim 15

A magnetic domain memory system comprising: a data chip including; a thin magnetic film suitable for use in generating magnetic domains, said layer of magnetic material being organized into open ended first and second major propagation paths suitably positioned adjacent to and operatively associated with a plurality of minor loops for storing said magnetic domains, transfer means for moving said magnetic domains from said first major propagation paths to said plurality of minor loops, replicate means disposed between said plurality of minor loops and said second major propagation paths for transferring magnetic domains from said minor loops to said second major propagation paths. means for detecting the presence of magnetic domains connected to and operatively associated with said second major propagation paths, dedicated minor loop disposed in parallel relation to said plurality of minor loops, for storing synchronization and redundancy data; and control means for propagating first and second magnetic domains around each of said major propagation paths and around said minor loops at a selected clock frequency and controlling transfer of magnetic domains between said minor loops and said first and second major propagation paths.

Claim 16

A magnetic domain memory system as set forth in claim 13, wherein said control means includes: synchronization data storage means and redundancy data storage means connected to said data chip, counter means for providing a signal for tracking the location of data stored in said plurality of minor loops, sequence timing means for providing signals to the data chip designating operational modes, and data buffers for storing data retrieved from said data chip for use by a data processor unit.

Claim 17

A magnetic domain memory system as set forth in claim 14, further including clock means for providing a signal to said data chip to initialize said redundancy data storage means.

Claim 18

A magnetic domain memory system as set forth in claim 14, wherein said synchronization data storage means and said redundancy data storage means comprise shift registers.

Claim 19

A magnetic domain memory system as set forth in claim 13 further including a plurality of said data chips.

Claim 20

A magnetic domain memory system as set forth in claim 17 further including a volatile memory means connected to said plurality of data chips and said control means.