← Back to Patent Explorer
US4158182A Expired / Lapsed US ⏱️ 0.0 years remaining

Low noise oscillator circuit

Assignee: Harris Corp
•
Filing: 1978-07-31
•
Granted: 1979-06-12
•
Expires: 1998-07-31
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A low noise, high frequency oscillator (50) is disclosed which includes a JFET (100) having a tuned circuit (102) connected in a feedback arrangement with it. The JFET is operated in a self-biasing mode and includes a gate biasing circuit (104) comprised of a capacitor (114) and a resistor (116). The capacitor (114) and resistor (116) are selected such that the gate bias circuit (104) represents a low impedance path to low frequency noise components. These low frequency noise components are therefore shunted to ground, and do not modulate the operation of the JFET (100). This significantly reduces noise in the oscillator output signal. A hot carrier diode (118) is connected across the gate-to-source junction of the JFET (100) to reduce loading on the tuned circuit (102) by the JFET (100).

Inventors

  • 👤 Clyde Washburn

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 19:55
CPC Classifications
H; H03; H03B; H03B5/00; H03B5/08; H03B5/12; H03B5/1228; H03B5/1203; H03B5/1237; H03B5/124; H03B5/1243; H03B2200/00; H03B2200/003; H03B2200/004; H03B2201/00; H03B2201/02; H03B2201/0208

Claims Analysis

Total Claims: 10
Claim 1
Independent Claim 123 words
A low noise high frequency oscillator comprising: a junction field effect semiconductor device having first and second electrodes defining therebetween a primary current path, and a gate electrode for controlling current flow between said first and second electrodes; a tuned circuit coupled between at least one of said first and second electrodes and said gate electrode; a gate bias circuit for providing a DC bias voltage to said gate electrode including a capacitor coupled between said gate electrode and a power supply connection, and a resistor connected to provide a DC current path across said capacitor, wherein said capacitor and resistor of said gate bias circuit have values selected so that said gate bias circuit has a low impedance at selected noise frequencies,
Claim 2
Dependent Claim 123 words
A low noise high frequency oscillator comprising: a junction field effect semiconductor device having first and second electrodes defining therebetween a primary current path, and a gate electrode for controlling current flow between said first and second electrodes; a tuned circuit coupled between at least one of said first and second electrodes and said gate electrode; a gate bias circuit for providing a DC bias voltage to said gate electrode including a capacitor coupled between said gate electrode and a power supply connection, and a resistor connected to provide a DC current path across said capacitor, wherein said capacitor and resistor of said gate bias circuit have values selected so that said gate bias circuit has a low impedance at selected noise frequencies,
Claim 3
Dependent Claim 76 words
A low noise, high frequency oscillator as set forth in claim 1 wherein said tuned circuit is coupled to said gate electrode from a point in said tuned circuit having a low impedance, DC coupling to a power supply connection, and wherein said capacitor of said gate biasing means is connected between said gate electrode and said point in said tuned circuit so as to provide said coupling of said tuned circuit to said gate electrode.
Claim 4
Dependent Claim 58 words
A low noise, high frequency oscillator as set forth in claim 1, wherein the junction between said gate electrode and one of said first and second electrodes provides peak rectification of the signal applied to said gate electrode by said tuned circuit, so as to thereby develop a biasing voltage across said capacitor of said gate biasing means.
Claim 5
Dependent Claim 63 words
A low noise, high frequency oscillator as set forth in claim 1, wherein a low stored-charge diode is connected between said gate electrode and one of said first and second electrodes and provides peak rectification of the signal applied to said gate electrode by said tuned circuit so as to thereby develop a biasing voltage across said capacitor of said gate biasing means.
Claim 6
Dependent Claim 22 words
A low noise, high frequency oscillator as set forth in claim 4, wherein said low stored-charge diode is a hot carrier diode.
Claim 7
Dependent Claim 22 words
A low noise, high frequency oscillator as set forth in claim 1, wherein said junction field effect semiconductor device comprises a JFET.
Claim 8
Dependent Claim 74 words
An RF signal source for use in a radio receiver or transmitter, comprising a self-biasing junction field effect semiconductor amplifier having a tuned circuit coupled in a feedback arrangement therewith so as to define a feedback oscillator, said amplifier having a gate biasing circuit comprised of a capacitor and a resistor, said resistor and capacitor having values selected so that said gate biasing circuit provides a low impedance path for low frequency noise components.
Claim 9
Dependent Claim 74 words
An RF signal source for use in a radio receiver or transmitter, comprising a self-biasing junction field effect semiconductor amplifier having a tuned circuit coupled in a feedback arrangement therewith so as to define a feedback oscillator, said amplifier having a gate biasing circuit comprised of a capacitor and a resistor, said resistor and capacitor having values selected so that said gate biasing circuit provides a low impedance path for low frequency noise components.
Claim 10
Dependent Claim 48 words
An RF signal source as set forth in claim 7, and further comprising means responsive to the RF signal generated by said feedback oscillator for providing an RF signal whose amplitude remains stable independently of variations in the amplitude of said RF signal generated by said feedback oscillator.

References Cited (Backward Citations)

US3281699A Cited
US3436681A Cited
US3534294A Cited
US3775698A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1982-06-11 1982-12-11 1983-06-12 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1986-06-11 1986-12-11 1987-06-12 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1990-06-11 1990-12-11 1991-06-12 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag